參數(shù)資料
型號(hào)： MPC8245LZU350X
廠商： MOTOROLA INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 350 MHz, RISC PROCESSOR, PBGA352
封裝： 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, CAVITY DOWN, TBGA-352
文件頁(yè)數(shù)： 31/60頁(yè)
文件大小： 620K
代理商： MPC8245LZU350X
MPC8245 Integrated Processor Hardware Specications
37
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Package Description
Notes:
1
Place a pull-up resistor of 120 Ohms or less on the TEST0 pin.
2
Treat these pins as No Connects unless using debug address functionality.
3
This pin has an internal pull-up resistor which is enabled only when the MPC8245 is in the reset state.
The value of the internal pull-up resistor is not guaranteed, but is sufcient to insure that a logic'1' is read
into conguration bits during reset.
4
This pin is a reset conguration pin.
5
DL[0] is a reset conguration pin and has an internal pull-up resistor which is enabled only when the
MPC8245 is in the reset state. The value of the internal pull-up resistor is not guaranteed, but is sufcient
to insure that a logic'1' is read into conguration bits during reset.
6
Multi-pin signals such as AD[31–0] or MDL[0–31] have their physical package pin numbers listed in order
corresponding to the signal names. Ex: AD0 is on pin C22, AD1 is on pin D22,... AD31 is on pin V25.
7
GNT4 is a reset conguration pin and has an internal pull-up resistor which is enabled only when the
MPC8245 is in the reset state.
8
Recommend a weak pull-up resistor (2K – 10K Ohm) be placed on this PCI control pin to LVdd.
9VIH and VIL for these signals are the same as the PCI VIH and VIL entries in Table 3.
10 Recommend a weak pull-up resistor (2K – 10K Ohm) be placed on this pin to OVdd.
11 Recommend a weak pull-up resistor (2K – 10K Ohm) be placed on this pin to GVdd.
12 This pin has an internal pull-up resistor which is enabled at all times. The value of the internal pull-up
resistor is not guaranteed, but is sufcient to prevent unused inputs from oating.
13 External PCI clocking source or fan-out buffer may be required for system if using the MPC8245 DUART
functionality since PCI_CLK[0–3] are not available in DUART mode. Only PCI_CLK4 is available in
DUART mode.
14 This pin is a multiplexed signal and appears more than once in this table.
15 This pin is affected by programmable PCI_HOLD_DEL parameter.
16 This pin is an open drain signal.
17 This pin can be programmed to be driven (default) or can be programmed (in PMCR2) to be open drain.
18 This pin is a Sustained Tri-State pin as dened by the PCI Local Bus Specication.
19 OSC_IN utilizes the 3.3V PCI interface driver which is 5V tolerant, see Table 2 for details.
20 PLL_CFG signals are sampled a few clocks after the negation of HRST_CPU and HRST_CTRL.
Debug/Manufacturing Pins
DA0/QACK
F2
Output
OVdd
DRV_STD
3,4,14
DA1/CKO
B15
Output
OVdd
DRV_STD
14
DA2
C25
Output
OVdd
DRV_PCI
2
DA3/PCI_CLK4
AF26
Output
GVdd
DRV_PCI_CLK
14
DA4/REQ4
Y26
I/O
OVdd
—
12,14
DA5/GNT4
W26
Output
OVdd
DRV_PCI
7,15,14
DA[10–6]/
PLL_CFG[0–4]
A22 B19 A21 B18 B17
I/O
OVdd
—
6,14,20
DA[11–13]
AD26 AF17 AF19
Output
OVdd
DRV_PCI
2,6
DA[14–15]
F1 J2
Output
GVdd
DRV_MEM_ADDR
2,6
Table 16. MPC8245 Pinout Listing (Continued)
Signal Name
Package Pin Number
Pin Type
Power
Supply
Output Driver Type
Notes
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