參數(shù)資料
型號: MPC8245LZU350X
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 350 MHz, RISC PROCESSOR, PBGA352
封裝: 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, CAVITY DOWN, TBGA-352
文件頁數(shù): 22/60頁
文件大?。?/td> 620K
代理商: MPC8245LZU350X
MPC8245 Integrated Processor Hardware Specications
29
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
Figure 19. EPIC Serial Interrupt Mode Input Timing Diagram
1.4.3.6 IEEE 1149.1 (JTAG) AC Timing Specications
Table 15 provides the JTAG AC timing specications for the MPC8245 while in the JTAG operating mode.
Notes:
1
TRST is an asynchronous signal. The setup time is for test purposes only.
2
Non-test (other than TDI and TMS) signal input timing with respect to TCK.
3
Non-test (other than TDO) signal output timing with respect to TCK.
4
Timings are independent of the system clock (PCI_SYNC_IN).
Table 15. JTAG AC Timing Specification (Independent of PCI_SYNC_IN)
At recommended operating conditions (see Figure 2) with LVdd = 3.3 V ± 0.3V
Num
Characteristic4
Min
Max
Unit
Notes
TCK Frequency of Operation
0
25
MHz
1
TCK Cycle Time
40
ns
2
TCK Clock Pulse Width Measured at 1.5 V
20
ns
3
TCK Rise and Fall Times
03
ns
4
TRST Setup Time to TCK Falling Edge
10
ns
1
5
TRST Assert Time
10
ns
6
Input Data Setup Time
5
ns
2
7
Input Data Hold Time
15
ns
2
8
TCK to Output Data Valid
030
ns
3
9
TCK to Output High Impedance
030
ns
3
10
TMS, TDI Data Setup Time
5—
ns
11
TMS, TDI Data Hold Time
15
ns
12
TCK to TDO Data Valid
015
ns
13
TCK to TDO High Impedance
015
ns
6
S_CLK
S_INT
7
VM
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