參數(shù)資料
型號(hào)： MPC8245LVV350D
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 350 MHz, RISC PROCESSOR, PBGA352
封裝： 35 X 35 MM, 1.27 MM PITCH, LEAD FREE, TBGA-352
文件頁(yè)數(shù)： 43/64頁(yè)
文件大小： 893K
代理商： MPC8245LVV350D
48
MPC8245 Integrated Processor Hardware Specifications
MOTOROLA
System Design Information
The programmable PCI output valid and output hold feature controlled by bits in the power management
configuration register 2 (PMCR2) <0x72> has changed slightly in the MPC8245. For the MPC8240, three
bits, PMCR2[6:4] = PCI_HOLD_DEL, are used to select 1 of 8 possible PCI output timing configurations.
PMCR2[6:5] are software-controllable but are initially set by the reset configuration state of the MCP and
CKE signals, respectively; PMCR2[4] can be changed by software. The default configuration for
PMCR2[6:4] = 0b110 since the MCP and CKE signals have internal pull-up resistors, but this default
configuration does not select 33- or 66-MHz PCI operation output timing parameters for the MPC8240; this
choice is made by software. For the MPC8245, only two bits in the power management configuration
register 2 (PMCR2), PMCR2[5:4] = PCI_HOLD_DEL, control the variable PCI output timing.
PMCR2[5:4] are software controllable but are initially set by the inverted reset configuration state of the
MCP and CKE signals, respectively. The default configuration for PMCR2[5:4] = 0b00 since the MCP and
CKE signals have internal pull-up resistors and the values from these signals are inverted; this default
configuration selects 66-MHz PCI operation output timing parameters. There are four programmable PCI
output timing configurations on the MPC8245, see Table 11 for details.
Voltage sequencing requirements for the MPC8245 are similar to those for the MPC8240; however, two
changes applicable to the MPC8245. First, there is an additional requirement for the MPC8245 that the
non-PCI input voltages (Vin) must not be greater than GVDD or OVDD by more than 0.6 V at all times,
including during power-on reset (see Caution 5 in Table 2). Second, for the MPC8245, LVDD must not
exceed OVDD by more than 3.0 V at any time, including during power-on reset (see Caution 10 in Table 2);
the allowable separation between LVDD and OVDD is 3.6 V for the MPC8240.
There is no LAVDD input voltage supply signal on the MPC8245 since the SDRAM clock delay-locked loop
(DLL) has power supplied internally. Signal D17 should be treated as a NC for the MPC8245.
1.7.7
JTAG Configuration Signals
Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the
IEEE 1149.1 specification but is provided on all processors that implement the PowerPC architecture. While
it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, more reliable
power-on reset performance can be obtained if the TRST signal is asserted during power-on reset. Because
the JTAG interface is also used for accessing the common on-chip processor (COP) function, simply tying
TRST to HRESET is not practical.
The COP function of these processors allows a remote computer system (typically, a PC with dedicated
hardware and debugging software) to access and control the internal operations of the processor. The COP
interface connects primarily through the JTAG port of the processor, with some additional status monitoring
signals. The COP port requires the ability to independently assert HRESET or TRST in order to fully control
the processor. If the target system has independent reset sources, such as voltage monitors, watchdog timers,
power supply failures, or push-button switches, the COP reset signals must be merged into these signals with
logic.
The arrangement shown in Figure 28 allows the COP to independently assert HRESET or TRST while
ensuring that the target can drive HRESET as well. If the JTAG interface and COP header will not be used,
TRST should be tied to HRESET so that it is asserted when the system reset signal (HRESET) is asserted
ensuring that the JTAG scan chain is initialized during power-on.
The COP header shown in Figure 28 adds many benefits—breakpoints, watchpoints, register and memory
examination/modification, and other standard debugger features are possible through this interface—and
can be as inexpensive as an unpopulated footprint for a header to be added when needed.
The COP interface has a standard header for connection to the target system based on the 0.025"
square-post, 0.100" centered header assembly (often called a Berg header).
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MPC8245LZU266D 功能描述:微處理器 - MPU 266MHz 505.4MIPS RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8245LZU300D 功能描述:微處理器 - MPU 300MHz 570MIPS RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8245LZU333D 功能描述:微處理器 - MPU 333MHz 632.7MIPS RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8245LZU350D 功能描述:微處理器 - MPU 350MHz 665MIPS RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8245RZU400D 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Part Number Specification for the MPC8245ARZUnnnX Series
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