參數(shù)資料
型號(hào): MPC8241LZP200X
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 200 MHz, RISC PROCESSOR, PBGA357
封裝: 25 X 25 MM, PLASTIC, BGA-357
文件頁數(shù): 21/56頁
文件大?。?/td> 739K
代理商: MPC8241LZP200X
28
MPC8241 Integrated Processor Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics
1.4.3.5
PIC Serial Interrupt Mode AC Timing Specifications
Table 15 provides the PIC serial interrupt mode AC timing specifications for the MPC8241 at recommended
operating conditions (see Table 2) with GVDD_OVDD =3.3 V ±5% and LVDD = 3.3 V ±0.3 V.
Figure 18. PIC Serial Interrupt Mode Output Timing Diagram
Table 15. PIC Serial Interrupt Mode AC Timing Specifications
Num
Characteristic
Min
Max
Unit
Notes
1
S_CLK frequency
1/14 SDRAM_SYNC_IN
1/2 SDRAM_SYNC_IN
MHz
1
2
S_CLK duty cycle
40
60
%
3
S_CLK output valid time
6
ns
4
Output hold time
0
ns
5S_FRAME, S_RST output valid time
1
sys_logic_clk period + 6
ns
2
6
S_INT input setup time to S_CLK
1
sys_logic_clk period + 2
ns
2
7
S_INT inputs invalid (hold time) to
S_CLK
—0
ns
2
Notes:
1. See the
MPC8245 Integrated Processor User’s Manual for a description of the PIC interrupt control register (ICR)
describing S_CLK frequency programming.
2. S_RST, S_FRAME, and S_INT shown in Figure 18 and Figure 19, depict timing relationships to
sys_logic_clk and
S_CLK and do not describe functional relationships between S_RST, S_FRAME, and S_INT. See the
MPC8245
Integrated Processor User’s Manual for a complete description of the functional relationships between these
signals.
3. The
sys_logic_clk waveform is the clocking signal of the internal peripheral logic from the output of the peripheral
logic PLL;
sys_logic_clk is the same as SDRAM_SYNC_IN when the SDRAM_SYNC_OUT to SDRAM_SYNC_IN
feedback loop is implemented and the DLL is locked. See the
MPC8245 Integrated Processor User’s Manual for a
complete clocking description.
S_CLK
S_RST
VM
S_FRAME
sys_logic_clk
VM
4
3
5
4
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