參數(shù)資料
型號: MPC7410RX500LX
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 500 MHz, RISC PROCESSOR, CBGA360
封裝: 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360
文件頁數(shù): 5/44頁
文件大小: 885K
代理商: MPC7410RX500LX
MPC7410 RISC Microprocessor Hardware Specifications
13
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
Figure 3 provides the SYSCLK input timing diagram.
Figure 3. SYSCLK Input Timing Diagram
1.4.2.2 Processor Bus AC Specifications
Table 9 provides the processor bus AC timing specifications for the MPC7410 as defined in Figure 4 and
Figure 5. Timing specifications for the L2 bus are provided in Section 1.4.2.3, “L2 Clock AC
Table 9. Processor Bus AC Timing Specifications1
At recommended operating conditions (See Table 3)
Parameter
Symbol2
400, 450, 500 MHz
Unit
Notes
Min
Max
Mode Select Input Setup to HRESET
tMVRH
8
—t
sysclk
3, 4, 5, 6
HRESET to Mode Select Input Hold
tMXRH
0
ns
2, 3, 5
Input Setup
tIVKH
1.0
ns
Input Hold
tIXKH
0—
ns
Output Valid Times:
TS
ARTRY, SHD0, SHD1
All Other Outputs
tKHTSV
tKHARV
tKHOV
3.0
2.3
3.0
ns
7, 8
Output Hold Times:
TS
ARTRY, SHD0, SHD1
All Other Outputs
tKHTSX
tKHARX
tKHOX
0.5
ns
7, 12
SYSCLK to Output Enable
tKHOE
0.5
ns
11
SYSCLK to Output High Impedance (all except
ABB/AMON(0), ARTRY/SHD, DBB/DMON(0), SHD0,
SHD1)
tKHOZ
—3.5
ns
SYSCLK to ABB/AMON(0), DBB/DMON(0) High
Impedance After Precharge
tKHABPZ
—1
t
sysclk
5, 9, 11
Maximum Delay to ARTRY, SHD0, SHD1 Precharge
tKHARP
—1
t
sysclk
5, 10, 11
SYSCLK to ARTRY, SHD0, SHD1 High Impedance
After Precharge
tKHARPZ
—2
t
sysclk
5, 10, 11
SYSCLK
VM
CVIH
CVIL
VM = Midpoint Voltage (OVDD/2)
tSYSCLK
tKR
tKF
tKHKL
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