參數(shù)資料
型號: MPC7410RX500LX
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 500 MHz, RISC PROCESSOR, CBGA360
封裝: 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360
文件頁數(shù): 4/44頁
文件大小: 885K
代理商: MPC7410RX500LX
12
MPC7410 RISC Microprocessor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
1.4.2 AC Electrical Characteristics
This section provides the AC electrical characteristics for the MPC7410. After fabrication, functional parts
are sorted by maximum processor core frequency as shown in Section 1.4.2.1, “Clock AC Specifications,”
and tested for conformance to the AC specifications for that frequency. The processor core frequency is
determined by the bus (SYSCLK) frequency and the settings of the PLL_CFG[0:3] signals. Parts are sold
by maximum processor core frequency; see Section 1.10, “Ordering Information.”
1.4.2.1 Clock AC Specifications
Table 8 provides the clock AC timing specifications as defined in Figure 3.
Table 8. Clock AC Timing Specifications
At recommended operating conditions (See Table 3)
Characteristic
Symbol
Maximum Processor Core Frequency
Unit
Notes
400 MHz
450 MHz
500 MHz
Min
Max
Min
Max
Min
Max
Processor frequency
fcore
350
400
350
450
350
500
MHz
1
VCO frequency
fVCO
450
800
450
900
450
1000
MHz
1
SYSCLK frequency
fSYSCLK
33
133
33
133
33
133
MHz
1
SYSCLK cycle time
tSYSCLK
7.5307.5
30
7.530
ns
SYSCLK rise and fall
time
tKR & tKF
0.5
0.5
0.5
ns/V
2
SYSCLK duty cycle
measured at OVdd/2
tKHKL/tSYSCLK
40
60
40
60
40
60
%
3
SYSCLK jitter
±150
±150
±150
ps
4
Internal PLL relock time
100
100
100
s5
Notes:
1. Caution: The SYSCLK frequency and PLL_CFG[0:3] settings must be chosen such that the resulting SYSCLK
(bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or
minimum operating frequencies. Refer to the PLL_CFG[0:3] signal description in Section 1.8.1, “PLL
Configuration,” for valid PLL_CFG[0:3] settings
2. Rise and fall times measurement are determined by the slew rates of the bus interface, rather than by time. As
a result, the 0.5 ns rise/fall time spec of the 1.8 V and 2.5 V bus interfaces is equivalent to the 1 ns rise/fall time
of the 3.3 V bus interface. Both interfaces required a 2 v/ns slew rate. The slew rate is measured as a 1-V
change (from 0.2 V to 1.2 V) in 0.5 ns for the 1.8 V and 2.5 V bus interfaces, whereas the 3.3-V bus interface
required a 2-V change (from 0.4 V to 2.4 V) in 1 ns.
3. Timing is guaranteed by design and characterization.
4. This represents total input jitter—short term and long term combined—and is guaranteed by design.
5. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time
required for PLL lock after a stable Vdd and SYSCLK are reached during the power-on reset sequence. This
specification also applies when the PLL has been disabled and subsequently re-enabled during sleep mode.
Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during
the power-on reset sequence.
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