參數(shù)資料
型號: MPC7410RX450LX
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 450 MHz, RISC PROCESSOR, CBGA360
封裝: 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360
文件頁數(shù): 25/44頁
文件大?。?/td> 885K
代理商: MPC7410RX450LX
MPC7410 RISC Microprocessor Hardware Specifications
31
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
System Design Information
1.8.2 PLL Power Supply Filtering
The AVdd and L2AVdd power signals are provided on the MPC7410 to provide power to the clock
generation phase-locked loop and L2 cache delay-locked loop, respectively. To ensure stability of the
internal clock, the power supplied to the AVdd input signal should be filtered of any noise in the 500 kHz
to 10 MHz resonant frequency range of the PLL. A circuit similar to the one shown in Figure 18 using
surface mount capacitors with minimum Effective Series Inductance (ESL) is recommended.
The circuit should be placed as close as possible to the AVdd pin to minimize noise coupled from nearby
circuits. An identical but separate circuit should be placed as close as possible to the L2AVdd pin. It is often
possible to route directly from the capacitors to the AVdd pin, which is on the periphery of the 360 CBGA
footprint, without the inductance of vias. The L2AVdd pin may be more difficult to route but is
proportionately less critical.
Figure 18. PLL Power Supply Filter Circuit
1.8.3 Power Supply Voltage Sequencing
The notes in Table 1 contain cautions about the sequencing of the external bus voltages and core voltage of
the MPC7410 (when they are different). These cautions are necessary for the long term reliability of the part.
If they are violated, the ESD (Electrostatic Discharge) protection diodes will be forward biased and
excessive current can flow through these diodes. If the system power supply design does not control the
voltage sequencing, the circuit of Figure 19 can be added to meet these requirements. The MUR420
Schottky diodes of Figure 19 control the maximum potential difference between the external bus and core
power supplies on power-up and the 1N5820 diodes regulate the maximum potential difference on
power-down.
500
333
250
200
166
143
125
Note:
1. The core and L2 frequencies are for reference only. Some examples may
represent core or L2 frequencies which are not useful, not supported, or not
tested for by the MPC7410; see Section 1.4.2.3, “L2 Clock AC Specifications,” for
valid L2CLK frequencies. The L2CR[L2SL] bit should be set for L2CLK
frequencies less than 150 MHz.
Table 15. Sample Core-to-L2 Frequencies (Continued)
Core Frequency
in MHz
÷1
÷1.5
÷2
÷2.5
÷3
÷3.5
÷4
Vdd
AVdd (or L2AVdd)
10
2.2 F
GND
Low ESL surface mount capacitors
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