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參數(shù)資料
| 型號： | MPC7410RX400NE |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 400 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件頁數(shù)： | 31/73頁 |
| 文件大?。?/td> | 929K |
| 代理商： | MPC7410RX400NE |
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MOTOROLA
MPC7410 RISC Microprocessor Hardware Specications
37
System Design Information
is not required by the MPC7410 (note that the MPC7410 always generates parity), then all parity pins may
be left unconnected by the system.
The L2 interface does not normally require pull-up resistors.
1.8.7
JTAG Conguration Signals
Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the
IEEE 1149.1 specication, but is provided on all processors that implement the PowerPC architecture.
While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, more
reliable power-on reset performance will be obtained if the TRST signal is asserted during power-on reset.
Because the JTAG interface is also used for accessing the common on-chip processor (COP) function,
simply tying TRST to HRESET is not practical.
The COP function of these processors allows a remote computer system (typically, a PC with dedicated
hardware and debugging software) to access and control the internal operations of the processor. The COP
interface connects primarily through the JTAG port of the processor, with some additional status monitoring
signals. The COP port requires the ability to independently assert HRESET or TRST in order to fully control
the processor. If the target system has independent reset sources, such as voltage monitors, watchdog timers,
power supply failures, or push-button switches, then the COP reset signals must be merged into these signals
with logic.
The arrangement shown in Figure 22 allows the COP port to independently assert HRESET or TRST, while
ensuring that the target can drive HRESET as well. If the JTAG interface and COP header will not be used,
TRST should be tied to HRESET through a 0-
isolation resistor so that it is asserted when the system reset
signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during power-on. While
Motorola recommends that the COP header be designed into the system as shown in Figure 22, if this is not
possible, the isolation resistor will allow future access to TRST in the case where a JTAG interface may need
to be wired onto the system in debug situations.
The COP header shown in Figure 22 adds many benets—breakpoints, watchpoints, register and memory
examination/modication, and other standard debugger features are possible through this interface—and
can be as inexpensive as an unpopulated footprint for a header to be added when needed.
The COP interface has a standard header for connection to the target system, based on the 0.025"
square-post 0.100" centered header assembly (often called a Berg header). The connector typically has
pin 14 removed as a connector key.
There is no standardized way to number the COP header shown in Figure 22; consequently, many different
pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then
left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter
clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in
Figure 22 is common to all known emulators.
The QACK signal shown in Figure 22 is usually connected to the PCI bridge chip in a system and is an input
to the MPC7410 informing it that it can go into the quiescent state. Under normal operation this occurs
during a low-power mode selection. In order for COP to work, the MPC7410 must see this signal asserted
(pulled down). While shown on the COP header, not all emulator products drive this signal. If the product
does not, a pull-down resistor can be populated to assert this signal. Additionally, some emulator products
implement open-drain type outputs and can only drive QACK asserted; for these tools, a pull-up resistor can
be implemented to ensure this signal is deasserted when it is not being driven by the tool. Note that the
pull-up and pull-down resistors on the QACK signal are mutually exclusive and it is never necessary to
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| MPC7410THX500LE | 32-BIT, 500 MHz, RISC PROCESSOR, CBGA360 |
| MPC7410RX400NE | 32-BIT, 400 MHz, RISC PROCESSOR, CBGA360 |
| MPC7410THX450LE | 32-BIT, 450 MHz, RISC PROCESSOR, CBGA360 |
| MPC7410TRX400NE | 32-BIT, 400 MHz, RISC PROCESSOR, CBGA360 |
| MPC7410THX400LE | 32-BIT, 400 MHz, RISC PROCESSOR, CBGA360 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC7410RX450NE | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MPC7410 RISC Microprocessor Hardware Specifications Addendum |
| MPC7410RX500LE | 功能描述:IC MPU 32BIT 500MHZ PPC 360-CBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:MPC74xx 標(biāo)準(zhǔn)包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點(diǎn):- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤 |
| MPC7410THX400LE | 功能描述:微處理器 - MPU NT HITCE RV1.4 1.8V -40C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC7410THX400NE | 制造商:Freescale Semiconductor 功能描述:MPU MPC74XX RISC 64BIT 0.18UM 400MHZ 1.8V/2.5V/3.3V 360FCCBG - Bulk |
| MPC7410THX450NE | 功能描述:微處理器 - MPU NT NITCE RV1.4,1.8V -40C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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