
36
MPC7410 RISC Microprocessor Hardware Specications
MOTOROLA
System Design Information
Table 15 summarizes the signal impedance results. The driver impedance values were characterized at 0°,
65°, and 105°C. The impedance increases with junction temperature and is relatively unaffected by bus
voltage.
1.8.6
Pull-Up Resistor Requirements
The MPC7410 requires pull-up resistors (1 k
–5 k) on several control pins of the bus interface to maintain
the control signals in the negated state after they have been actively negated and released by the MPC7410
or other bus masters. These pins are: TS, ARTRY, SHDO, SHD1.
Four test pins also require pull-up resistors (100
1 k). These pins are CHK, L1_TSTCLK,
L2_TSTCLK, and LSSD_MODE. These signals are for factory use only and must be pulled up to
OVDD for normal machine operation.
If pull-down resistors are used to congure BVSEL or L2VSEL, the resistors should be less than 250
(see
Table 12). Because PLL_CFG[0:3] must remain stable during normal operation, strong pull-up and
pull-down resistors (1 k
or less) are recommended to congure these signals in order to protect against
erroneous switching due to ground bounce, power supply noise or noise coupling.
In addition, CKSTP_OUT is an open-drain style output that requires a pull-up resistor (1 k
–5 k) if it is
used by the system. The CKSTP_IN signal should likewise be pulled up through a pull-up resistor
(1 k
–5 k) to prevent erroneous assertions of this signal.
During inactive periods on the bus, the address and transfer attributes may not be driven by any master and
may, therefore, oat in the high-impedance state for relatively long periods of time. Since the MPC7410
must continually monitor these signals for snooping, this oat condition may cause excessive power draw
by the input receivers on the MPC7410 or by other receivers in the system. These signals can be pulled up
through weak (10-k
) pull-up resistors by the system, address bus driven mode can be enabled (see the
MPC7410 RISC Microporcessor Family Users’ Manual for more information on this mode), or these
signals may be otherwise driven by the system during inactive periods of the bus to avoid this additional
power draw. The snooped address and transfer attribute inputs are: A[0:31], AP[0:3], TT[0:4], CI, WT, and
GBL.
In systems where GBL is not connected and other devices may be asserting TS for a snoopable transaction
while not driving GBL to the processor, we recommend that a strong (1 k
) pull-up resistor be used on
GBL. Note that the MPC7410 will only snoop transactions when GBL is asserted.
The data bus input receivers are normally turned off when no read operation is in progress and, therefore,
do not require pull-up resistors on the bus. Other data bus receivers in the system, however, may require
pull-ups, or that those signals be otherwise driven by the system during inactive periods by the system. The
data bus signals are: DH[0:31], DL[0:31], and DP[0:7].
If address or data parity is not used by the system, and the respective parity checking is disabled through
HID0, the input receivers for those pins are disabled, and those pins do not require pull-up resistors and
should be left unconnected by the system. If parity checking is disabled through HID0, and parity generation
Table 15. Impedance Characteristics
VDD = 1.8 V, OVDD = 2.5 V, Tj = 0° – 105°C
Impedance
Processor Bus
L2 Bus
Symbol
Unit
RN
41.5–54.3
42.7–54.1
Z0
RP
37.3–55.3
39.3–50.0
Z0