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參數(shù)資料
| 型號： | MPC740ARX266TX |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 266 MHz, RISC PROCESSOR, CBGA255 |
| 封裝： | 21 X 21 MM, 3 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-255 |
| 文件頁數(shù)： | 40/44頁 |
| 文件大?。?/td> | 558K |
| 代理商： | MPC740ARX266TX |
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MPC750A RISC Microprocessor Hardware Specications
5
Features
— 3 cycle latency, 1 cycle throughput, double-precision add
— 4 cycle latency, 2 cycle throughput, double-precision multiply-add
— Hardware support for divide
— Hardware support for denormalized numbers
— Time deterministic non-IEEE mode
System unit
— Executes CR logical instructions and miscellaneous system instructions
— Special register transfer instructions
Cache structure
— 32K, 32-byte line, 8-way set associative instruction cache
— 32K, 32-byte line, 8-way set associative data cache
— Single-cycle cache access
— Pseudo-LRU replacement
— Copy-back or write-through data cache (on a page per page basis)
— Supports all PowerPC memory coherency modes
— Non-blocking instruction and data cache (one outstanding miss under hits)
— No snooping of instruction cache
Memory management unit
— 128 entry, 2-way set associative instruction TLB
— 128 entry, 2-way set associative data TLB
— Hardware reload for TLBs
— 4 instruction BATs and 4 data BATs
— Virtual memory support for up to 4 exabytes (252) of virtual memory
— Real memory support for up to 4 gigabytes (232) of physical memory
Level 2 (L2) cache interface (not implemented on MPC740)
— Internal L2 cache controller and 4K-entry tags; external data SRAMs
— 256K, 512K, and 1 Mbyte 2-way set associative L2 cache support
— Copy-back or write-through data cache (on a page basis, or for all L2)
— 64-byte (256K/512K) and 128-byte (1-Mbyte) sectored line size
— Supports ow-through (reg-buf) synchronous burst SRAMs, pipelined (reg-reg) synchronous
burst SRAMs, and pipelined (reg-reg) late-write synchronous burst SRAMs
— Core-to-L2 frequency divisors of ÷1, ÷1.5, ÷2, ÷2.5, and ÷3 supported
Bus interface
— Compatible with 60x processor interface
— 32-bit address bus
— 64-bit data bus
— Bus-to-core frequency multipliers of 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x, 8x
supported
Integrated power management
— Low-power 2.6/3.3-volt design
— Three static power saving modes: doze, nap, and sleep
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For More Information On This Product,
Go to: www.freescale.com
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