參數(shù)資料
型號： MPC740ARX266TX
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 266 MHz, RISC PROCESSOR, CBGA255
封裝： 21 X 21 MM, 3 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-255
文件頁數(shù)： 28/44頁
文件大?。?/td> 558K
代理商： MPC740ARX266TX
34
MPC750A RISC Microprocessor Hardware Specications
System Design Information
These capacitors should vary in value from 220 pF to 10
F to provide both high- and low-frequency
ltering, and should be placed as close as possible to their associated Vdd or OVdd pins. Suggested values
for the Vdd pins—220 pF (ceramic), 0.01 F (ceramic), and 0.1 F (ceramic). Suggested values for the
OVdd pins—0.01 F (ceramic), 0.1 F (ceramic), and 10 F (tantalum). Only SMT (surface mount
technology) capacitors should be used to minimize lead inductance.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the Vdd and OVdd planes, to enable quick recharging of the smaller chip capacitors. These bulk
capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick response time
necessary. They should also be connected to the power and ground planes through two vias to minimize
inductance. Suggested bulk capacitors—100 F (AVX TPS tantalum) or 330 F (AVX TPS tantalum).
1.8.4 Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to Vdd. Unused active high inputs should be connected to
GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external Vdd, OVdd, and GND pins of the MPC750.
External clock routing should ensure that the rising-edge of the L2 clock is coincident at the CLK input of
all SRAMs and at the L2SYNC_IN input of the MPC750. The L2CLKOUTA network could be used only,
or the L2CLKOUTB network could also be used depending on the loading, frequency, and number of
SRAMs.
1.8.5 Output Buffer DC Impedance
The MPC750 60x and L2 I/O drivers were characterized over process, voltage, and temperature. To
measure Z0, an external resistor is connected to the chip pad, either to OVdd or OGND. Then, the value of
such resistor is varied until the pad voltage is OVdd/2; see Figure 19.
The output impedance is actually the average of two components, the resistances of the pull-up and
pull-down devices. When Data is held low, SW1 is closed (SW2 is open), and RN is trimmed until
Pad = OVdd/2. RN then becomes the resistance of the pull-down devices. When Data is held high, SW2 is
closed (SW1 is open), and RP is trimmed until Pad = OVdd/2. RP then becomes the resistance of the
pull-up devices. With a properly designed driver RP and RN are close to each other in value. Then Z0 = (RP
+ RN)/2.
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For More Information On This Product,
Go to: www.freescale.com
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