參數(shù)資料
型號(hào)： MPC740ARX233LX
廠商： MOTOROLA INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 233 MHz, RISC PROCESSOR, CBGA255
封裝： 21 X 21 MM, 3 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-255
文件頁(yè)數(shù)： 8/44頁(yè)
文件大?。?/td> 280K
代理商： MPC740ARX233LX
16
MPC750A RISC Microprocessor Hardware Specications
Electrical and Thermal Characteristics
Internal DLL-relock time
640
—
L2CLK
3
L2CLKOUT output-to-output skew
50
ps
5
L2CLKOUT output jitter
150
ps
5
Notes:
1. L2CLK outputs are L2CLK_OUTA, L2CLK_OUTB and L2SYNC_OUT pins. The L2 cache interface supports higher frequencies
when appropriate load conditions have been considered. The L2 I/O drivers have been designed to support a 133 MHz L2 bus
loaded with 4 off-the-shelf pipelined synchronous burst SRAMs. Running the L2 bus beyond 133 MHz requires tightly coupled
customized SRAMs or a multi-chip module (MCM) implementation. The L2CLK frequency to core frequency settings must be
chosen such that the resulting L2CLK frequency and core frequency do not exceed their respective maximum or minimum
operating frequencies. L2CLK_OUTA and L2CLK_OUTB must have equal loading.
2. The nominal duty cycle of the L2CLK is 50% measured at midpoint voltage.
3. The DLL re-lock time is specified in terms of L2CLKs. The number in the table must be multiplied by the period of L2CLK to
compute the actual time duration in nanoseconds. Re-lock timing is guaranteed by design and characterization.
4. The L2CR[L2SL] bit should be set for L2CLK frequencies less than 110 MHz
5. Guaranteed by design and not tested.
Table 11. L2CLK Output AC Timing Specifications (Continued)
At recommended operating conditions (See Table 3)
Num
Characteristic
Min
Max
Unit
Notes
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