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參數(shù)資料
| 型號： | MPC740ARX233LX |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 233 MHz, RISC PROCESSOR, CBGA255 |
| 封裝： | 21 X 21 MM, 3 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-255 |
| 文件頁數(shù)： | 44/44頁 |
| 文件大?。?/td> | 280K |
| 代理商： | MPC740ARX233LX |
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MPC750A RISC Microprocessor Hardware Specications
9
Electrical and Thermal Characteristics
Table 6 provides the DC electrical characteristics for the MPC750.
Table 7 provides the power consumption for the MPC750.
Table 6. DC Electrical Specifications
At recommended operating conditions (See Table 3)
Characteristic
Symbol
Min
Max
Unit
Notes
Input high voltage (all inputs except SYSCLK)
VIH
1.7
L2OVdd + 0.3
V
2,3,4
VIH
2
OVdd + 0.3
V
2,3,
Input low voltage (all inputs except SYSCLK)
VIL
-0.3
0.2 * L2OVdd
V
4
VIL
-0.3
0.8
V
SYSCLK input high voltage
CVIH
2.4
OVdd + 0.3
V
2
SYSCLK input low voltage
CVIL
-0.3
0.4
V
Input leakage current, Vin = OVdd
Iin
—
30
A
2,3
Hi-Z (off-state) leakage current, Vin = OVdd
ITSI
—
30
A
2,3,6
Output high voltage, IOH = -6 mA
VOH
1.8
—
V
VOH
2.4
—
V
Output low voltage, IOL = 6 mA
VOL
—
0.4
V
Capacitance, Vin = 0 V, f = 1 MHz
Cin
—
5.0
pF
3,5
Notes:
1. Nominal voltages; See Table 3 for recommended operating conditions.
2. For 60x bus signals, the reference is OVdd while L2OVdd is the reference for the L2 bus signals.
3. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK) and IEEE 1149.1 boundary scan (JTAG) signals.
4. Applicable to L2 bus interface only
5. Capacitance is periodically sampled rather than 100% tested.
6. The leakage is measured for nominal OVdd and Vdd, or both OVdd and Vdd must vary in the same direction (for example, both
OVdd and Vdd vary by either +5% or -5%).
Table 7. Power Consumption for MPC750
Processor (CPU) Frequency
Unit
Notes
200 MHz
233 MHz
266 MHz
Full-On Mode
Typical
Maximum
4.2
5.0
5.7
W
1, 3, 4
6.0
7.0
7.9
W
1, 2, 4
Doze Mode
Maximum
1.6
1.8
2.1
W
1, 2
Nap Mode
Maximum
250
mW
1, 2
Sleep Mode
Maximum
300
mW
1, 2
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