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參數(shù)資料
| 型號(hào)： | MPC7400RX333LX |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 333 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件頁數(shù)： | 29/44頁 |
| 文件大小： | 504K |
| 代理商： | MPC7400RX333LX |
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MPC7400 RISC Microprocessor Hardware Specications
35
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
System Design Information
Table 16 summarizes the signal impedance results. The driver impedance values were characterized at 0°C,
65 °C, and 105 °C. The impedance increases with junction temperature and is relatively unaffected by bus
voltage.
1.8.7 Pull-up Resistor Requirements
The MPC7400 requires high-resistive (weak: 10 K
) pull-up resistors on several control pins of the bus
interface to maintain the control signals in the negated state after they have been actively negated and
released by the MPC7400 or other bus masters. These pins are TS, ARTRY, SHDO, and SHD1.
In addition, the MPC7400 has one open-drain style output that requires a pull-up resistor (weak or stronger:
4.7 K
–10 K) if it is used by the system. This pin is CKSTP_OUT.
During inactive periods on the bus, the address and transfer attributes may not be driven by any master and
may therefore oat in the high-impedance state for relatively long periods of time. Since the MPC7400 must
continually monitor these signals for snooping, this oat condition may cause excessive power draw by the
input receivers on the MPC7400 or by other receivers in the system. It is recommended that these signals
be pulled up through weak (10 K
) pull-up resistors by the system, or that they may be otherwise driven by
the system during inactive periods of the bus. The snooped address and transfer attribute inputs are:
A[0:31], AP[0:3], TT[0:4], and GBL.
The data bus input receivers are normally turned off when no read operation is in progress and therefore do
not require pull-up resistors on the bus. Other data bus receivers in the system, however, may require
pullups, or that those signals be otherwise driven by the system during inactive periods by the system. The
data bus signals are: D[0:63], DP[0:7]
If address or data parity is not used by the system, and the respective parity checking is disabled through
HID0, the input receivers for those pins are disabled, and those pins do not require pull-up resistors and
should be left unconnected by the system. If all parity generation is disabled through HID0, then all parity
checking should also be disabled through HID0, and all parity pins may be left unconnected by the system.
The L2 interface does not normally require pull-up resistors.
1.8.8 JTAG Conguration Signals
Boundary scan testing is enabled through the JTAG interface signals. (BSDL descriptions of the MPC7400
are available on the internet at www.mot.com/PowerPC/teksupport.) The TRST signal is optional in the
IEEE 1149.1 specication but is provided on all PowerPC implementations. While it is possible to force the
TAP controller to the reset state using only the TCK and TMS signals, more reliable power-on reset
performance will be obtained if the TRST signal is asserted during power-on reset. Since the JTAG interface
is also used for accessing the common on-chip processor (COP) function of PowerPC processors, simply
tying TRST to HRESET isn’t practical.
The common on-chip processor (COP) function of PowerPC processors allows a remote computer system
(typically a PC with dedicated hardware and debugging software) to access and control the internal
operations of the processor. The COP interface connects primarily through the JTAG port of the processor,
with some additional status monitoring signals. The COP port requires the ability to independently assert
Table 16. Impedance Characteristics
Vdd = 1.8V, OVdd = 3.3V, Tj = 0 - 105 °C
Impedance
Processor bus
L2 bus
Symbol
Unit
RN
32-43
39-48
Z0
Ohms
RP
36-48
41-50
Z0
Ohms
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