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參數(shù)資料
| 型號： | MPC7400RX333LX |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 333 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件頁數(shù)： | 26/44頁 |
| 文件大?。?/td> | 504K |
| 代理商： | MPC7400RX333LX |
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32
MPC7400 RISC Microprocessor Hardware Specications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
System Design Information
The MPC7400 generates the clock for the external L2 synchronous data SRAMs by dividing the core clock
frequency of the MPC7400. The divided-down clock is then phase-adjusted by an on-chip delay-lock-loop
(DLL) circuit and should be routed from the MPC7400 to the external RAMs. A separate clock output,
L2SYNC_OUT is sent out half the distance to the SRAMs and then returned as an input to the DLL on pin
L2SYNC_IN so that the rising-edge of the clock as seen at the external RAMs can be aligned to the clocking
of the internal latches in the L2 bus interface.
The core-to-L2 frequency divisor for the L2 PLL is selected through the L2CLK bits of the L2CR register.
Generally, the divisor must be chosen according to the frequency supported by the external RAMs, the
frequency of the MPC7400 core, and the phase adjustment range that the L2 DLL supports. Table 15 shows
various example L2 clock frequencies that can be obtained for a given set of core frequencies. The minimum
L2 frequency target is 100MHz.
1.8.2 PLL Power Supply Filtering
The AVdd and L2AVdd power signals are provided on the MPC7400 to provide power to the clock
generation phase-locked loop and L2 cache delay-locked loop respectively. To ensure stability of the
internal clock, the power supplied to the AVdd input signal should be ltered of any noise in the 500kHz to
10MHz resonant frequency range of the PLL. A circuit similar to the one shown in Figure 18 using surface
mount capacitors with minimum Effective Series Inductance (ESL) is recommended.
1111
PLL off
PLL off, no core clocking occurs
Notes:
1. PLL_CFG[0–3] settings not listed are reserved.
2. The sample bus-to-core frequencies shown are for reference only. Some PLL congurations may select
bus, core, or VCO frequencies which are not useful, not supported, or not tested for by the MPC7400;
see Section 1.4.2.1, “Clock AC Specications,” for valid SYSCLK, core, and VCO frequencies.
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is
disabled, and the bus mode is set for 1:1 mode operation. This mode is intended for factory use only.
Note: The AC timing specications given in this document do not apply in PLL-bypass mode.
4. In PLL-off mode, no clocking occurs inside the MPC7400 regardless of the SYSCLK input.
Table 15. Sample Core-to-L2 Frequencies
Core Frequency in MHz
÷1
÷1.5
÷2
÷2.5
÷3
÷3.5
÷4
300
200
150
120
100
—
333
222
166
133
111
—
350
—
175
140
117
100
—
366
—
183
147
122
105
—
400
—
200
160
133
114
100
Note:
1. The core and L2 frequencies are for reference only. Some examples may represent core or L2
frequencies which are not useful, not supported, or not tested for by the MPC7400; see
Section 1.4.2.3, “L2 Clock AC Specications,” for valid L2CLK frequencies. The
L2CR[L2SL] bit should be set for L2CLK frequencies less than 110 MHz.
Table 14. MPC7400 Microprocessor PLL Configuration (Continued)
PLL_CFG
[0–3]
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)
Bus-to-
Core
Multiplier
Core-to
VCO
Multiplier
Bus
25 MHz
Bus
33.3
MHz
Bus
50 MHz
Bus
66.6
MHz
Bus
75 MHz
Bus
100 MHz
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