參數(shù)資料
型號(hào): MPC5668GF0AVMGR
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 116 MHz, MICROCONTROLLER, PBGA208
封裝: 17 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, MO151AAF-1, MAPBGA-208
文件頁(yè)數(shù): 39/66頁(yè)
文件大?。?/td> 889K
代理商: MPC5668GF0AVMGR
MPC5668x Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
Electrical Characteristics
Freescale Semiconductor
44
4.14.3
JTAG (IEEE 1149.1) Interface
Figure 9. JTAG Test Clock Input Timing
Table 26. JTAG Interface Timing1
1 These specifications apply to JTAG boundary scan only. JTAG timing specified at V
DDE =3.0–5.5V, TA =TL to TH, and
CL = 30 pF with SRC = 0b11.
Spec
Characteristic
Symbol
Min
Max
Unit
1
TCK Cycle Time
tJCYC
100
ns
2
TCK Clock Pulse Width (Measured at VDDE/2)
tJDC
40
60
ns
3
TCK Rise and Fall Times (40% – 70%)
tTCKRISE
—3
ns
4
TMS, TDI Data Setup Time
tTMSS, tTDIS
5—
ns
5
TMS, TDI Data Hold Time
tTMSH, tTDIH
25
ns
6
TCK Low to TDO Data Valid
tTDOV
—25
ns
7
TCK Low to TDO Data Invalid
tTDOI
0—
ns
8
TCK Low to TDO High Impedance
tTDOHZ
—20
ns
9
JCOMP Assertion Time
tJCMPPW
100
ns
10
JCOMP Setup Time to TCK Low
tJCMPS
40
ns
11
TCK Falling Edge to Output Valid
tBSDV
—50
ns
12
TCK Falling Edge to Output Valid out of High Impedance
tBSDVZ
—50
ns
13
TCK Falling Edge to Output High Impedance
tBSDHZ
—50
ns
14
Boundary Scan Input Valid to TCK Rising Edge
tBSDST
50
ns
15
TCK Rising Edge to Boundary Scan Input Invalid
tBSDHT
50
ns
TCK
1
2
3
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MPC5668x
products
in
208
and
256
MAPBGA
packages
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