MPC561/MPC563 Reference Manual, Rev. 1.2
RegIndex-2
Freescale Semiconductor
MI_RA 1 - 3 (region base address registers (1 - 3))
MI_RBA 0 - 3 (region base address registers (0 - 3))
MIOS
bus interface (MBISM) Registers
MIOS1
interrupt level register 0 (MIOSLVL0) (MIOS1LVL0)
interrupt level register 1 (MIOSLVL1) (MIOS1LVL0)
module and version number register (MIOS1VNR)
MIOS14ER0 interrupt enable register
MIOS14ER1 interrupt enable register
MIOS14MCR (MIOS14 module configuration register)
MIOS14RPR0 request pending register
MIOS14RPR1 request pending register
MIOS14SR0 (interrupt status register)
MIOS14SR0 interrupt status register
MIOS14SR1 (interrupt status register)
MIOS14SR1 interrupt status register
MIOS14TPCR (test and pin control register)
MIOS1LVL0 (MIOS1 interrupt level register 0)
MIOS1LVL1 (MIOS1 interrupt level 1 register)
MISCNT (MISC counter)
MISRH (multiple input signature register high)
MISRL (multiple input signature register low)
MMCSMCNT (MMCSM up-counter register)
MMCSMMML (MMCSM modulus latch register)
MMCSMSCR (MMCSM status/control register)
MPIOSMDDR (MPIOSM data direction register)
MPIOSMDR (MPIOSM data register)
MPWMCNTR (MPWMSM counter register)
MPWMPERR (MPWMSM period register)
MPWMPULR (MPWMSM pulse width register)
MPWMSCR (MPWMSM status/control register)
MSTAT (memory controller status registers)
10-32
O
OR0 - OR3 (memory controller option registers 0-3)
P
PDMCR (pads module configuration register)
PDMCR2 (pads module configuration register)
PISCR (periodic interrupt status and control register)
PITC (periodic interrupt timer count register)
PITR (periodic interrupt timer register)
PLPRCR (PLL, low-power, and reset-control register)
Port data direction registers
Port data registers
PORTQS (port QS data register)
PPMMCR (module configuration register)
PPMPCR (PPM control register)
PQSPAR (PORTQS pin assignment register)
PRESDIV (prescaler divide register)
Q
QACR0 (QADC64E control register 0)
QACR1 (QADC64E control register 1)
QACR2 (QADC64E control register 2)
QADCINT (QADC64E interrupt register)
QADCMCR (module configuration register)
QASR (status register 0)
QASR (status registers)
QSCI1CR (QSCI1 control register)
QSCI1SR (QSCI1 status register)
QSMCM
configuration register (QMCMMCR)
interrupt level registers (QDSCI_IL, QSPI_IL)
port QS data register (PORTQS)
PORTQS data direction register (DDRQS)
PORTQS pin assignment register (PQSPAR)
QSCI1 control register (QSCI1CR)
QSCI1 status register (QSCI1SR)
QSPI command RAM (CRx)
QSPI control register 0 (SPCR0)
QSPI control register 1 (SPCR1)
QSPI control register 2 (SPCR2)
QSPI control register 3 (SPCR3)
QSPI registers
QSPI status register (SPSR)
queued SCI1 status and control registers
SCI control register 0 (SCCxR0)
SCI control register 1 (SCCxR1)
SCI data register (SCxDR)
SCI registers
SCI status register (SCxSR)
test register (QTEST)
QSMCMMCR (QSMCM module configuration register)
QSPI_IL (QSPI interrupt level register)
R
RCPU
additional implementation-specific registers
condition register (CR)
condition register CR0 field definition
condition register CR1 field definition
condition register crn field - compare instruction
count register (CTR)
dae/source instruction service register (DSISR)
data address register (DAR)
decrementer register (DEC)
EIE, EID, and NRI special-purpose registers