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| 型號(hào)： | MPC5602PEFMLL |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, MS-026BED, LQFP-100 |
| 文件頁數(shù)： | 1/72頁 |
| 文件大小： | 661K |
| 代理商： | MPC5602PEFMLL |
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MAPBGA–225
15 mm x 15 mm
QFN12
##_mm_x_##mm
LQFP100 (14 x 14 x 1.4 mm)
LQFP144 (20 x 20 x 1.4 mm)
Freescale Semiconductor
Data Sheet: Advance Information
Document Number: MPC5604P
Rev. 1, 8/2008
Freescale Semiconductor, Inc., 2008. All rights reserved.
Preliminary—Subject to Change Without Notice
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
MPC560xP
MPC560xP Microcontroller
Data Sheet
32-bit Power Architecture based MCU for
Automotive Chassis and Safety Applications
Single issue, 32-bit Power Architecture CPU core complex
(e200z0h) with Harvard architecture
– Provides variable length encoding (VLE) instruction set
encoding for code size footprint reduction
– With the encoding of mixed 16-bit and 32-bit
instructions, it is possible to achieve significant code
size footprint reduction over conventional Book E
compliant code
Up to 512 KB on-chip code flash memory with ECC plus
64 KB on-chip data flash with ECC
Up to 40 KB SRAM on-chip with ECC
Interrupt controller (INTC) capable of handling 144
selectable-priority interrupt sources
Up to two FMPLL modules
Clock Monitor Unit (CMU) to monitor the integrity of the
main crystal oscillator and the PLL and act as a frequency
meter, measuring the frequency of one clock source and
comparing it to a reference clock
16 MHz internal RC Oscillator (RCOSC) (trimmable)
Four Periodic Interrupt Timers (PITs) with 32-bit counter
resolution
Windowed software watchdog (SWT)
Output compare system timer (STM) to support
AUTOSAR task protection
Crossbar switch (XBAR) architecture for concurrent
access to peripherals, flash memory or RAM from multiple
bus masters (AMBA 2.0 v6 AHB)
16-channel Enhanced Direct Memory Access (eDMA)
controller with multiple transfer request sources using
DMA MUX
System Integration Unit (SIU) Lite; controls the GPIO
mode of the pads, the pads alternate function, and the pads
configuration
Boot assist module (BAM) supports downloading
operation to internal SRAM via serial link (FlexCAN or
LINFlex or FlexRay)
FlexPWM motor control PWM module (1 x 8 PWM
channels)
Two enhanced eTimer timer modules (six channels each)
with dedicated motor control and quadrature decode
features integrated
Safety Port to support functional safety architectures on the
ECU level. Can be optionally used as a second FlexCAN
module with 32 message buffers.
Two independent 10-bit analog-to-digital converters
(ADCs) with a conversion time target of 700 ns for the
analog section. Each converter supports 16 channels
(ADC0: channel 15 dedicated to the Temperature sensor;
ADC1: channel 15 for the internal 1.2 V rail; channels 11
to 14 shared between the two converters)
FlexPWM to ADC and eTimer Cross Triggering Unit
(CTU)
Fault Collection Unit (FCU) for functional safety
Four Serial Peripheral Interface (DSPI) modules
Two Serial Communication Interface (LINFlex) modules
with LIN support
FlexCAN Controller Area Network module with 32
message buffers
Dual channel FlexRay
Controller with 32 message
buffers (512 KB device only)
GPIO
– 144-pin package: 82 general-purpose pins supporting
input/output operations plus 26 general-purpose pins
supporting input operations (108 in total). Out of these
108 pins, 32 have external interrupt capability.
– 100-pin package: 51 general-purpose pins supporting
input/output operations plus 16 general-purpose pins
supporting input operations (67 in total). Out of these 67
pins, 25 have external interrupt capability.
Nexus development interface (NDI) per IEEE-ISTO
5001-2003 standard Class 2+
JTAG (IEEE 1149.1) 4-pin interface
Voltage regulator (VREG) for regulation into 3.3 V - 5 V
input down to 1.2 V nominal core logic level with external
transistor
Embedded junction temperature sensor
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