參數(shù)資料
型號(hào): MPC5200VR400
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 74/80頁(yè)
文件大?。?/td> 0K
描述: IC MPU 32BIT 400MHZ PPC 272-PBGA
標(biāo)準(zhǔn)包裝: 40
系列: MPC52xx
核心處理器: 603e G2 LE
芯體尺寸: 32-位
速度: 400MHz
連通性: CAN,EBI/EMI,以太網(wǎng),I²C,IrDA,J1850,SPI,UART/USART,USB
外圍設(shè)備: AC'97,DMA,I²S,POR,PWM,WDT
輸入/輸出數(shù): 56
程序存儲(chǔ)器類(lèi)型: 外部程序存儲(chǔ)器
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.42 V ~ 1.58 V
振蕩器型: 內(nèi)部
工作溫度: 0°C ~ 70°C
封裝/外殼: 272-BBGA
包裝: 托盤(pán)
MPC5200 Data Sheet, Rev. 4
System Design Information
Freescale Semiconductor
76
For a board with a COP (common on-chip processor) connector, which accesses the JTAG interface and
which needs to reset the JTAG module, simply wiring JTAG_TRST and PORRESET is not recommended.
To reset the MPC5200 via the COP connector, the HRESET pin of the COP should be connected to the
HRESET pin of the MPC5200. The circuitry shown in Figure 55 allows the COP to assert HRESET or
JTAG_TRST separately, while any other board sources can drive PORRESET.
8—
N/C
7
JTAG_TCK
tck
100k Pull-Up
10k Pull-Up
O
6—
VDD2
——
5
See Note 3.halted3
——
I
4JTAG_TRST
trst
100k Pull-Up
10k Pull-Up
O
3
JTAG_TDI
tdi
100k Pull-Up
10k Pull-Up
O
2
See Note 4.
qack4
——
O
1JTAG_TDO
tdo
I
NOTES:
1
With respect to the emulator tool’s perspective:
Input is really an output from the embedded G2_LE core.
Output is really an input to the core.
2
From the board under test, power sense for chip power.
3
HALTED is not available from G2_LE core.
4
Input to the G2_LE core to enable/disable soft-stop condition during breakpoints. MPC5200
internal ties core_qack_ to GND in its normal/functional mode (always asserted).
Table 53. COP/BDM Interface Signals (continued)
BDM
Pin #
MPC5200
I/O Pin
BDM
Connector
Internal
PullUp/Down
External
PullUp/Down
I/O1
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