(t)LI 0150" />
參數(shù)資料
型號: MPC5200VR400
廠商: Freescale Semiconductor
文件頁數(shù): 31/80頁
文件大?。?/td> 0K
描述: IC MPU 32BIT 400MHZ PPC 272-PBGA
標(biāo)準(zhǔn)包裝: 40
系列: MPC52xx
核心處理器: 603e G2 LE
芯體尺寸: 32-位
速度: 400MHz
連通性: CAN,EBI/EMI,以太網(wǎng),I²C,IrDA,J1850,SPI,UART/USART,USB
外圍設(shè)備: AC'97,DMA,I²S,POR,PWM,WDT
輸入/輸出數(shù): 56
程序存儲器類型: 外部程序存儲器
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.42 V ~ 1.58 V
振蕩器型: 內(nèi)部
工作溫度: 0°C ~ 70°C
封裝/外殼: 272-BBGA
包裝: 托盤
Electrical and Thermal Characteristics
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
37
(t)LI
015001500150
Limited Interlock time.1,2
A8.34
(t)MLI
20
20
20
Interlock time with minimum.1,2
A8.35
(t)UI
0
0
0
Unlimited interlock time. 1,2
A8.36
(t)AZ
10
10
10
Maximum time allowed for output drivers to release
from being asserted or negated
A8.37
(t)ZAH
20
20
20
Minimum delay time required for output drivers to
assert or negate from released state
A8.38
(t)ZAD
0—0—0—
A8.39
(t)ENV
20
70
20
70
20
70
Envelope time—from DMACK to STOP and
HDMARDY during data out burst initiation.
A8.40
(t)SR
50
30
20
STROBE to DMARDY time, if DMARDY is negated
before this long after STROBE edge, the recipient
receives no more than one additional data word.
A8.41
(t)RFS
75
60
50
Ready-to-Final STROBE time—no STROBE edges
are sent this long after negation of DMARDY.
A8.42
(t)RP
160
125
100
Ready-to-Pause time—the time recipient waits to
initiate pause after negating DMARDY.
A8.43
(t)IORDYZ
20
20
20
Pull-up time before allowing IORDY to be released.
A8.44
(t)ZIORDY
0
0
0
Minimum time drive waits before driving IORDY
A8.45
(t)ACK
20
20
20
Setup and hold times for DMACK, before assertion or
negation.
A8.46
(t)SS
50
50
50
Time from STROBE edge to negation of DMARQ or
assertion of STOP, when sender terminates a burst.
A8.47
NOTES:
1
tUI, tMLI, tLI indicate sender-to-recipient or recipient-to-sender interlocks. That is, one agent (either sender or recipient)
is waiting for the other agent to respond with a signal before proceeding.
tUI is an unlimited interlock that has no maximum time value.
tMLI is a limited time-out that has a defined minimum.
tLI is a limited time-out that has a defined maximum.
2
All timing parameters are measured at the connector of the drive to which the parameter applies. For example, the
sender shall stop generating STROBE edges tRFS after negation of DMARDY. Both STROBE and DMARDY timing
measurements are taken at the connector of the sender. Even though the sender stops generating STROBE edges,
the receiver may receive additional STROBE edges due to propagation delays. All timing measurement switching
points (low to high and high to low) are taken at 1.5 V.
Table 29. Ultra DMA Timing Specification (continued)
Name
MODE 0
(ns)
MODE 1
(ns)
MODE 2
(ns)
Comment
SpecID
Min
Max
Min
Max
Min
Max
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