參數(shù)資料
型號(hào): MPC5200VR400
廠(chǎng)商: Freescale Semiconductor
文件頁(yè)數(shù): 48/80頁(yè)
文件大?。?/td> 0K
描述: IC MPU 32BIT 400MHZ PPC 272-PBGA
標(biāo)準(zhǔn)包裝: 40
系列: MPC52xx
核心處理器: 603e G2 LE
芯體尺寸: 32-位
速度: 400MHz
連通性: CAN,EBI/EMI,以太網(wǎng),I²C,IrDA,J1850,SPI,UART/USART,USB
外圍設(shè)備: AC'97,DMA,I²S,POR,PWM,WDT
輸入/輸出數(shù): 56
程序存儲(chǔ)器類(lèi)型: 外部程序存儲(chǔ)器
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.42 V ~ 1.58 V
振蕩器型: 內(nèi)部
工作溫度: 0°C ~ 70°C
封裝/外殼: 272-BBGA
包裝: 托盤(pán)
MPC5200 Data Sheet, Rev. 4
Electrical and Thermal Characteristics
Freescale Semiconductor
52
NOTE
Output timing was specified at a nominal 50 pF load.
Figure 37. Timing Diagram—I2C Input/Output
3.3.14 J1850
See the MPC5200 User Manual [1].
Table 41. I2C Output Timing Specifications—SCL and SDA
Sym
Description
Min
Max
Units
SpecID
11
NOTES:
1
Programming IFDR with the maximum frequency (IFDR=0x20) results in the minimum output timings listed. The
I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period. The actual
position is affected by the prescale and division values programmed in IFDR.
Start condition hold time
6
IP-Bus Cycle3
A13.8
21
Clock low period
10
IP-Bus Cycle3
A13.9
32
2
Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL
or SDA takes to reach a high level depends on external signal capacitance and pull-up resistor values
SCL/SDA rise time
7.9
ns
A13.10
Data hold time
7
IP-Bus Cycle3
A13.11
SCL/SDA fall time
7.9
ns
A13.12
Clock high time
10
IP-Bus Cycle3
A13.13
Data setup time
2
IP-Bus Cycle3
A13.14
Start condition setup time (for repeated start condition
only)
20
IP-Bus Cycle3
A13.15
Stop condition setup time
10
IP-Bus Cycle3
3
Inter Peripheral Clock is defined in the MPC5200 User Manual [1].
A13.16
1
2
3
4
5
6
78
9
SCL
SDA
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