參數(shù)資料
型號(hào): MPC5200VR400
廠商: Freescale Semiconductor
文件頁數(shù): 18/80頁
文件大?。?/td> 0K
描述: IC MPU 32BIT 400MHZ PPC 272-PBGA
標(biāo)準(zhǔn)包裝: 40
系列: MPC52xx
核心處理器: 603e G2 LE
芯體尺寸: 32-位
速度: 400MHz
連通性: CAN,EBI/EMI,以太網(wǎng),I²C,IrDA,J1850,SPI,UART/USART,USB
外圍設(shè)備: AC'97,DMA,I²S,POR,PWM,WDT
輸入/輸出數(shù): 56
程序存儲(chǔ)器類型: 外部程序存儲(chǔ)器
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.42 V ~ 1.58 V
振蕩器型: 內(nèi)部
工作溫度: 0°C ~ 70°C
封裝/外殼: 272-BBGA
包裝: 托盤
Electrical and Thermal Characteristics
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
25
3.3.5.4
Memory Interface Timing-DDR SDRAM Write Command
Figure 9. DDR SDRAM Memory Write Timing
3.3.6
PCI
The PCI interface on the MPC5200 is designed to PCI Version 2.2 and supports 33-MHz and 66-MHz PCI
operations. See the PCI Local Bus Specification [4]; the component section specifies the electrical and
timing parameters for PCI components with the intent that components connect directly together whether
on the planar or an expansion board, without any external buffers or other “glue logic.” Parameters apply
at the package pins, not at expansion board edge connectors.
The MPC5200 is always the source of the PCI CLK. The clock waveform must be delivered to each
33-MHz or 66-MHz PCI component in the system. Figure 10 shows the clock waveform and required
measurement points for 3.3 V signaling environments. Table 22 summarizes the clock specifications.
Table 21. DDR SDRAM Memory Write Timing
Sym
Description
Min
Max
Units
SpecID
tmem_clk
MEM_CLK period
7.5
ns
A5.20
tDQSS
Delay from write command to first
rising edge of MDQS
—tmem_clk+0.4
ns
A5.21
MEM_CLK
Control Signals
MDQ (Data)
MEM_CLK
MDQS (Data Strobe)
NOTE: Control Signals signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN
Write
tdqss
Write
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