參數(shù)資料
型號(hào): MPC5200BV400
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: MPC5200 Hardware Specifications
中文描述: 400 MHz, RISC PROCESSOR, PBGA272
封裝: 27 X 27 MM, 1.27 MM PITCH, PLASTIC, BGA-272
文件頁(yè)數(shù): 25/76頁(yè)
文件大小: 1404K
代理商: MPC5200BV400
MOTOROLA
MPC5200 Hardware Specifications
25
Electrical and Thermal Characteristics
3.3.6 PCI
The PCI interface on the MPC5200 is designed to PCI Version 2.2 and supports 33-MHz and 66-MHz PCI
operations. See the PCI Local Bus Specification [4]; the component section specifies the electrical and
timing parameters for PCI components with the intent that components connect directly together whether
on the planar or an expansion board, without any external buffers or other “glue logic.” Parameters apply at
the package pins, not at expansion board edge connectors.
The MPC5200 is always the source of the PCI CLK. The clock waveform must be delivered to each
33-MHz or 66-MHz PCI component in the system.
Figure 9
shows the clock waveform and required
measurement points for 3.3 V signaling environments.
Table 22
summarizes the clock specifications.
Figure 9 PCI CLK Waveform
NOTES:
1.
In general, all 66-MHz PCI components must work with any clock frequency up to 66 MHz. CLK requirements vary de-
pending upon whether the clock frequency is above 33 MHz.
Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the
minimum peak-to-peak portion of the clock waveform as shown in
Figure 9
.
The minimum clock period must not be violated for any single clock cycle, i.e., accounting for all system jitter.
2.
3.
Table 22 PCI CLK Specifications
Sym
Description
66 MHz
33 MHz
Units
Notes
SpecID
Min
Max
Min
Max
T
cyc
PCI CLK Cycle Time
15
30
30
ns
1,3
A6.1
T
high
PCI CLK High Time
6
11
ns
A6.2
t
low
PCI CLK Low Time
6
A6.3
-
PCI CLK Slew Rate
1.5
4
1
4
V/ns
2
A6.4
Table 23 PCI Timing Parameters
Sym
Description
66 MHz
33 MHz
Units
Notes
SpecID
Min
Max
Min
Max
T
val
CLK to Signal Valid Delay -
bused signals
2
6
2
11
ns
1,2,3
A6.5
T
val
(ptp) CLK to Signal Valid Delay -
point to point
2
6
2
12
ns
1,2,3
A6.6
T
on
Float to Active Delay
2
2
ns
1
A6.7
T
off
Active to Float Delay
14
28
ns
1
A6.8
T
cyc
PCI CLK
T
low
T
high
0.6Vcc
0.4Vcc
0.3Vcc
0.4Vcc, p-to-p
(minimum)
0.5Vcc
0.2Vcc
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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