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參數(shù)資料
| 型號： | MPC505 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| 中文描述： | 32-BIT, RISC MICROCONTROLLER, PQFP16 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 68K |
| 代理商： | MPC505 |
Application Note
AN1281
2
MOTOROLA
Interrupt Basics
The PowerPCarchitecture uses unique vector offsets for “exceptions”
from normal processing. When an exception occurs, a hardware context
switch takes place and processing branches to the appropriate
exception vector address. The address is the sum of the vector offset
plus a physical base address of either 0x0000 0000 or 0xFFF0 0000 as
determined by the IP bit in the machine status register (MSR). In this
note, use of the 0x0000 0000 base address is assumed.
Table 1
shows
types of exceptions and associated vectors.
There is a difference in terminology between Motorola and IBM
PowerPC literature. Motorola uses the term
exception
to mean any
event which causes the processor to transfer control to one of the vector
addresses in the range 0xxxx0 0000 to 0xxxx0 3FFF, as well as to mean
theactiontakenbytheprocessorinresponsetosuchanevent.Theterm
interrupt
is used by Motorola to refer to events and the corresponding
processor responses which are associated with offset 0x00500.
IBM uses the term
exception
to refer to the event and the term
interrupt
to refer to the action taken by the processor in response to any
exception, independent of the vector address. Thus, IBM literature
describes floating point overflow as a floating point exception, which
PowerPC is a trademark of International Business Machines Corporation
.
Table 1. Exceptions and Vectors
Exception Type
Vector Offset
Reserved
0x00000
System reset
0x00100
Machine check
0x00200
Reserved
0x00300
Reserved
0x00400
Interrupts
0x00500
Alignment
0x00600
etc.
etc.
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