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參數(shù)資料
| 型號(hào)： | MPC505 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| 中文描述： | 32-BIT, RISC MICROCONTROLLER, PQFP16 |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 68K |
| 代理商： | MPC505 |
Application Note
Summary
AN1281
MOTOROLA
11
Housekeeping
Items and Return
Before exiting the interrupt service routine, a number of housekeeping
items must be performed:
1.
Clear the pending interrupt condition which set the bit in the
IRQPEND register.
2.
If the PIT caused the interrupt, clear the PIT status (PS) bit in
PICSR.
3.
If the interrupt was caused by an external interrupt pin in edge-
detect mode, clear the corresponding status bit in the port Q edge
detect/data (PQEDGDAT) register by first reading the bit as a one
and then writing it to a zero.
4.
Restore any previously used GPR (e.g. GPR4 used above).
5.
In case a non-maskable exception occurred during this interrupt
source routine,
a.
Disable the recoverable interrupt (RI) bit in the MSR by writing
any value to the NRI register:
mtspr
NRI, gpr0
Restore SRR0, SRR1 (and stack pointer if it changed).
b.
6.
Execute the return from interrupt instruction (which also enables
interrupts again):
rfi
Summary
With proper assignment of sources to levels, the MPC505 interrupt
controller provides an efficient priority mechanism. The interrupt level
can also be used as an offset to provide a branch to the appropriate
handler routine. Key issues a system designer must address include
handling non-maskable exceptions while interrupts are disabled,
handler data storage, and the length of time interrupts are disabled.
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