Tables of Signals
Signal and Connection Descriptions
Preliminary
21
Figure 7. MMC2080 Signal Group Organization
BREQ
BGNT
MPD[7:0]/D[15:8]
D[7:0]
A[21:0]
EB0–1
BW8
WE
OE
TA
ABORT
BUSCLK
SEL0–3
XBOOT
IRQ
D[31:16]
DVLEB0–1
DVL0–1
DVLSEL
DSTAT0–5
DVLMX
TC0–2
TEA
HIGHZ
PULL_EN
LOBAT
EXTS0–1
CLKOUT
SYMCLK
S1–7
S0/IFIN
MPE4/LOCK
MPE3/MOSI
MPE2/MISO
MPE1/SS
MPE0/SCLK
MPC7/URXD
MPC6/UTXD
MPC5/UCTS
MPC4/URTS
UCLK
MPC3/TIC1
MPC2/TOC1
MPC1/TIC0
MPC0/TOC0
MLDY
MPB[7:4]/ROW[3:0]
MPB[3:0]/COL[3:0]
MPA[5:0]
VDD
RESET
RSTOUT
TMS
TCK
TDI
TDO
TRST
DE
EXTAL
XTAL
CXFC
VDDCORE[5]
VSSCORE[5]
IOVDD[11]
IOVSS[11]
OSCVDD
OSCVSS
PLLVDD
PLLVSS
Arbitration
Signals
FLEX
Signals
Development
Extensions
(208-Pin
Package)
External
System
Bus
Signals
Arbitration Request
Arbitration Grant
High-Order Data Bus
Low-Order Data Bus
Address
Byte Enable
Bus Width (8-Bit)
Data Direction
Output Enable
Transfer Acknowledge
Data Transfer Abort
External Bus Clock
External Device Select
External Boot
Interrupt Request
Extension
Byte Enable
Development Mode
Development Select
Development Status
Status Output Select
Transfer Code
Transfer Error Acknowledge
Tri-State Disable
Pull-up Enable
Show Cycle Strobe
Low Battery
Extension Symbol
Clock Output
Symbol Clock
Serial Port
Serial Port
Synthesizer Lock
Master in/Slave Out
Master Out/Slave In
Slave Select
Serial Clock
Receive Data
Transmt Data
Clear-To-Send
Request-To-Send
UART Clock
Timer1 Input Capture
Timer1 Output Capture
Timer0 Input Capture
Timer0 Output Capture
Generator Waveform
Row Detect
Column Detect
Master Reset
Reset Output
Test Mode Select
Test Clock
Test Data In
Test Data Out
TAP Reset
Debug Enable
Oscillator Circuit Input
Oscillator Circuit Output
PLL Filter Capacitor
Core Power
Core Ground
I/O Pad Power
I/O Pad Ground
Oscillator Power
Oscillator Ground
PLL Power
PLL Ground
MMC2080
FSC/SPI
Signals
Timer
Signals
Melody
Generator
Signal
Keypad
Signals
MPIO
Signals
SIM
Signals
JTAG/OnCE
Signals
Clock
and
Power
SCI
Signals
SHS