參數(shù)資料
型號: MMBF4393LT3
廠商: ON SEMICONDUCTOR
元件分類: 小信號晶體管
英文描述: 30 V, N-CHANNEL, Si, SMALL SIGNAL, JFET, TO-236AB
封裝: CASE 318-08, 3 PIN
文件頁數(shù): 3/4頁
文件大小: 0K
代理商: MMBF4393LT3
MMBF4391LT1 MMBF4392LT1 MMBF4393LT1
http://onsemi.com
511
Figure 5. Switching Time Test Circuit
Figure 6. Typical Forward Transfer Admittance
Figure 7. Typical Capacitance
ID, DRAIN CURRENT (mA)
2.0
5.0
3.0
7.0
0.5
1.0
3.0
7.0
5.0
50
30
10
20
0.7
2.0
10
20
,FOR
W
ARD
TRANSFER
ADMITT
ANCE
(mmhos)
fs
V
10
2.0
15
3.0
5.0
7.0
0.5 1.0
3.0
30
5.0
0.3
0.1
10
0.05
0.03
VR, REVERSE VOLTAGE (VOLTS)
C,
CAP
ACIT
ANCE
(pF)
Tchannel = 25°C
VDS = 15 V
Tchannel = 25°C
(Cds is negligible
Cgs
-VDD
VGG
RGG
RT
RGEN
50
VGEN
RK
RD
OUTPUT
INPUT
50
SET VDS(off) = -10 V
INPUT PULSE
tr ≤ 0.25 ns
tf ≤ 0.5 ns
PULSE WIDTH = 2.0 s
DUTY CYCLE ≤ 2.0%
RGG > RK
RD' = RD(RT + 50)
RD + RT + 50
Figure 8. Effect of Gate–Source Voltage
on Drain–Source Resistance
80
120
160
200
50
1.0
3.0
170
5.0
20
-10
-40
2.0
80
140
-70
VGS, GATE-SOURCE VOLTAGE (VOLTS)
r
4.0
0
40
100 mA
125 mA
75 mA
50 mA
25 mA
IDSS
= 10
mA
Tchannel = 25°C
Figure 9. Effect of Temperature on Drain–Source
On–State Resistance
1.8
1.0
2.0
1.2
1.4
1.6
0.8
0.6
0.4
ID = 1.0 mA
VGS = 0
,DRAIN-SOURCE
ON-ST
AT
E
DS(on)
RESIST
ANCE
(NORMALIZED)
Tchannel, CHANNEL TEMPERATURE (°C)
1.5
1.0
Cgd
110
6.0
7.0
8.0
0
r
,DRAIN-SOURCE
ON-ST
AT
E
DS(on)
RESIST
ANCE
(OHMS)
MMBF4393
MMBF4392
MMBF4391
NOTE 1
The switching characteristics shown above were measured using
a test circuit similar to Figure 5. At the beginning of the switching
interval, the gate voltage is at Gate Supply Voltage (–VGG). The
Drain–Source Voltage (VDS) is slightly lower than Drain Supply
Voltage (VDD) due to the voltage divider. Thus Reverse Transfer
Capacitance (Crss) of Gate–Drain Capacitance (Cgd) is charged to
VGG + VDS.
During the turn–on interval, Gate–Source Capacitance (Cgs) dis-
charges through the series combination of RGen and RK. Cgd must
discharge to VDS(on) through RG and RK in series with the parallel
combination of effective load impedance (R’D) and Drain–Source
Resistance (rDS). During the turn–off, this charge flow is reversed.
Predicting turn–on time is somewhat difficult as the channel re-
sistance rDS is a function of the gate–source voltage. While Cgs dis-
charges, VGS approaches zero and rDS decreases. Since Cgd dis-
charges through rDS, turn–on time is non–linear. During turn–off,
the situation is reversed with rDS increasing as Cgd charges.
The above switching curves show two impedance conditions;
1) RK is equal to RD’ which simulates the switching behavior of
cascaded stages where the driving source impedance is normally
the load impedance of the previous stage, and 2) RK = 0 (low im-
pedance) the driving source impedance is that of the generator.
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