參數(shù)資料
型號： MM908E626R2
廠商： 飛思卡爾半導體(中國)有限公司
元件分類： 基準電壓源/電流源
英文描述： Integrated Stepper Motor Driver with Embedded MCU and LIN Serial Communication
中文描述： 集成的步進電機驅(qū)動器，帶有嵌入式微控制器和LIN串行通信
文件頁數(shù)： 27/32頁
文件大?。?/td> 303K
代理商： MM908E626R2
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
908E626
27
CLS2:CLS0—H-Bridge Current Limitation Selection Bits
These read/write bits select the current limitation value
according to
Table 3
. Reset clears the CLS2:CLS0 bits.
Table 3. H-Bridge Current Limitation Value Selection Bits
Switchable VDD Outputs
The HVDD terminal is a switchable VDD output terminal. It
can be used for driving external circuitry that requires a V
DD
voltage. The output is enabled with bit PSON in the System
Control Register and can be switched on/off with bit HVDDON
in the Power Output Register. Low- or high-voltage conditions
(LVI/HVI) have no influence on this circuitry.
HVDD Overtemperature Protection
Overtemperature protection is enabled if the high-
temperature reset is enabled.
HVDD Overcurrent Protection
The HVDD output is protected against overcurrent. In the
event the overcurrent limit is or was reached, the output
automatically switches off and the HVDD overcurrent flag in the
System Status Register is set.
System Control Register (SYSCTL)
PSON—Power Stages On Bit
This read/write bit enables the power stages (half-bridges,
LIN transmitter and HVDD output). Reset clears the PSON bit.
1 = Power stages enabled.
0 = Power stages disabled.
SRS0:SRS1—LIN Slew Rate Selection Bits
These read/write bits enable the user to select the
appropriate LIN slew rate for different baud rate configurations
as shown in
Table 4
.
The high speed slew rates are used, for example, for
programming via the LIN and are not intended for use in the
application.
Table 4. LIN Slew Rate Selection Bits
System Status Register (SYSSTAT)
LINCL — LIN Current Limitation Bit
This read-only bit is set if the LIN transmitter operates in
current limitation region. Due to excessive power dissipation in
the transmitter, software is advised to turn the transmitter off
immediately.
1 = Transmitter operating in current limitation region.
0 = Transmitter not operating in current limitation region.
HVDD_OCF—HVDD Output Overcurrent Flag Bit
This read/write flag is set on an overcurrent condition at the
HVDD terminal. Clear HVDD_OCF and enable the output by
writing a logic [1] to the HVDD_OCF Flag. Reset clears the
HVDD_OCF bit. Writing a logic [0] to HVDD_OCF has no effect.
1 = Overcurrent condition on HVDD has occurred.
0 = No overcurrent condition on HVDD has occurred.
LVF—Low-Voltage Bit
This read only bit is a copy of the LVF bit in the Interrupt Flag
Register.
1 = Low-voltage condition has occurred.
0 = No low-voltage condition has occurred.
HVF—High-Voltage Sensor Bit
This read-only bit is a copy of the HVF bit in the Interrupt Flag
Register.
1 = High-voltage condition has occurred.
0 = No high-voltage condition has occurred.
CLS2
CLS1
CLS0
Current Limit
0
0
0
No Limit
0
0
1
0
1
0
0
1
1
55 mA (typ)
1
0
0
260 mA (typ)
1
0
1
370 mA (typ)
1
1
0
550 mA (typ)
1
1
1
740 mA (typ)
Register Name and Address: SYSCTL - $03
Bit7
6
5
4
3
2
1
Bit0
Read
PSON
SRS1
SRS0
0
0
0
0
0
(Note 17)
Write
Reset
0
0
0
0
0
0
0
0
Notes
18.
This bit must always be set to 0.
SRS1
SRS0
LIN Slew Rate
0
0
Initial Slew Rate (20 kBaud)
0
1
Slow Slew Rate (10 kBaud)
1
0
High Speed II (8x)
1
1
High Speed I (4x)
Register Name and Address: SYSSTAT - $0c
Bit7
6
5
4
3
2
1
Bit0
Read
0
LINCL
HVDD
_OCF
0
LVF
HVF
HB_
OCF
HTF
Write
Reset
0
0
0
0
0
0
0
0
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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