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| 型號： | MM908E626R2 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Integrated Stepper Motor Driver with Embedded MCU and LIN Serial Communication |
| 中文描述： | 集成的步進電機驅(qū)動器，帶有嵌入式微控制器和LIN串行通信 |
| 文件頁數(shù)： | 20/32頁 |
| 文件大小： | 303K |
| 代理商： | MM908E626R2 |
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908E626
20
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Master Address Byte
A4:A0
Contains the address of the desired register.
R/
W
Contains information about a read or a write operation.
If R/
W
= 1, the second byte of master contains no valid
information, slave just transmits back register data.
If R/
W
= 0, the master sends data to be written in the
second byte, slave sends concurrently contents of
selected register prior to write operation, write data is
latched in the
SMARTMOS
register on rising edge of
SS
.
Parity P
The parity bit is equal to “0” if the number of 1 bits is an even
number contained within R/
W
,A4:A0. If the number of 1 bits is
odd, P equals “1”. For example, if R/
W
= 1, A4:A0 = 00001,
then P equals “0.”
The parity bit is only evaluated during a write operation.
Bit X
Not used.
Master Data Byte
Contains data to be written or no valid data during a read
operation.
Slave Status Byte
Contains the contents of the System Status Register ($0c)
independent of whether it is a write or read operation or which
register was selected.
Slave Data Byte
Contains the contents of selected register. During a write
operation it includes the register content prior to a write
operation.
SPI Register Overview
Table 1
summarizes the SPI Register addresses and the bit
names of each register.
Table 1. List of Registers
Addr
Register Name
R/W
Bit
7
6
5
4
3
2
1
0
$01
H-Bridge Output
(HBOUT)
R
HB4_H
HB4_L
HB3_H
HB3_L
HB2_H
HB2_L
HB1_H
HB1_L
W
$02
H-Bridge Control
(HBCTL)
R
OFC_EN
CSA
0
0
0
CLS2
CLS1
CLS0
W
$03
System Control
(SYSCTL)
R
PSON
SRS1
SRS0
0
0
0
0
0
W
$04
Interrupt Mask
(IMR)
R
0
0
LINIE
HTIE
LVIE
HVIE
OCIE
0
W
$05
Interrupt Flag
(IFR)
R
0
0
LINF
HTF
LVF
HVF
OCF
0
W
$06
Reset Mask
(RMR)
R
TTEST
0
0
0
0
0
HVRE
HTRE
W
$07
Analog Multiplexer
Configuration (ADMUX)
R
0
0
0
0
SS3
SS2
SS1
SS0
W
$08
Reserved
R
0
0
0
0
0
0
0
0
W
$09
Reserved
R
0
0
0
0
0
0
0
0
W
$0a
AWD Control
(AWDCTL)
R
0
0
0
AWDRE
0
0
AWDF
AWDR
W
AWDRST
$0b
Power Output
(POUT)
R
0
0
0
0
0
0
HVDDON
0
W
$0c
System Status
(SYSSTAT)
R
0
LINCL
HVDD_OCF
0
LVF
HVF
HB_OCF
HTF
W
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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