參數(shù)資料
型號(hào)： ML60851ETB
廠商： OKI ELECTRIC INDUSTRY CO LTD
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP44
封裝： 10 X 10 MM, 0.80 MM PITCH, PLASTIC, TQFP-44
文件頁(yè)數(shù)： 77/88頁(yè)
文件大小： 1137K
代理商： ML60851ETB
Oki Semiconductor
ML60851E
77/84
Operation of 2-layer structure FIFO during bulk transfer
The FIFOs of EP1 have a 64 bytes x 2-layer structure. As a consequence, these FIFOs can temporarily store a
maximum of 128 bytes of bulk transfer data.
(1) 2-Layer reception operation (O indicates the assert condition and X indicates de-assert condition)
The following description assumes that interrupt has been enabled for EP1 (D1 of INTENBL=1)
In the case of 1
→2→3→4→5a→6
In the case of 1
→2→3→4→5b→6
Layer A
64 bytes
Layer B
64 bytes
Layer A
PKT
RDY
Layer B
PKT
RDY
EP1
receive
PKT
RDY
INTR
1
Start storing data in layer A of reception
×
2
Data of one packet has been stored.
×
3
Start reception and storing of data in
layer B.
×
4
Local MCU starts reading layer A.
×
5a
When the storing of packet in layer B is
completed following the completion of
reading layer A.
5b
When the reading of packet in layer A
is completed following the completion
of storing data in layer B.
changed
×
6
From 5a: Layer A has become empty.
From 5b: Layer B has become full.
×
7
Starting reading layer B also.
×
When one packet of receive data is stored in layer A of the FIFO and EOP is received, the ML60851E asserts
the packet ready bit of EP1 and also asserts the
INTR pin. This makes it possible for the local MCU to read the
receive data.
Subsequently, data can be received from the host, and the ML60851E switches the FIFO for storing to layer B.
When one packet of data described above has been read from layer A of the FIFO, make the local MCU reset
the receive packet ready status of EP1 (by writing a “1” into bit D1 of PKTRDY).
At the time the EP1 receive packet ready status is reset, if the reception of layer B has not been completed, the
ML60851E resets the EP1 receive packet ready status and de-asserts the
INTR pin.
However, if the reception of layer B has been completed at the time the EP1 receive packet ready status is reset,
the ML60851E rejects the request from the local MCU to reset the EP1 receive packet ready status, and
continues to maintain the EP1 receive packet ready status and the asserted condition of the
INTR pin.
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