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參數(shù)資料
| 型號： | ML60851ETB |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 |
| 封裝： | 10 X 10 MM, 0.80 MM PITCH, PLASTIC, TQFP-44 |
| 文件頁數(shù)： | 31/88頁 |
| 文件大?。?/td> | 1137K |
| 代理商： | ML60851ETB |
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Oki Semiconductor
ML60851E
35/84
End Point 1 control Register (EP1CON)
Read address
E4h
Write address
64h
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
1
0
x
0
After a bus reset
0
1
0
x
0
Definition
0
1
0
Configuration Bit:
The local MCU should write “1” in this bit during the status stage of control transfer
when a “Set Configuration” request is received from the host computer to make EP1
active.
When this bit is “1”, the exchange of data between the host computer and EP1 is
enabled. When this bit is “0”, this IC does not respond to any transactions with this
EP.
Stall Bit:
When a data packet is received with a number of bytes more than the maximum
packet size set in the EP1 payload register, the ML60851E automatically sets this bit
to “1”. It is also possible for the local MCU to write a “1” in this bit. When this bit is
“1”, the stall handshake is automatically returned to the host computer in response to
the packet transmitted by the host computer to the end point. In addition, the packet
ready status is not asserted and even the
INTR pin is not asserted.
EP1 transfer type is set as bulk transfer and the end point address is 1h. Therefore, the bits D6 to D2 have fixed
values, and other values written in them are ignored.
Configuration Bit (R/W)
Stall Bit (R/W)
Transfer Type
10 = Bulk Transfer
End point Address (R)
Transfer Direction (R/W)
0 = Receive, 1 = Transmit
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