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參數(shù)資料
| 型號： | MK2049-03SI |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 49.152 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封裝： | 0.300 INCH, SOIC-20 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 136K |
| 代理商： | MK2049-03SI |
MK2049-02/03
Communications Clock PLLs
MDS 2049-02/03 C
6
Revision 091801
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126 (408)295-9800tel www.icst.com
OPERATING MODES (continued)
and E3 inputs, CLK1 will be 1/2 the input frequency and CLK2 will be the same as the input frequency.
Buffer Mode
Unlike the other two modes that accept only a single specified input frequency, Buffer Mode will accept a wider range
of input clocks. The input jitter is attenuated, and the outputs on CLK1 and CLK2 also provide the option of getting
x1, x2, x4, or 1/2 of the input frequency. For example, this mode can be used to remove the jitter from a 27 MHz
clock, generating low-jitter 27 MHz and 13.5 MHz outputs.
INPUT AND OUTPUT SYNCHRONIZATION
As shown in the tables on pages 4 and 5, the MK2049-02/03 offer a Zero Delay feature in most selections. In these
selections, there is an internal feedback path between ICLK and the CLK2 output clock. This provides a fixed phase
relationship between the input and output, a requirement in many communications systems.
MK2049-02
As illustrated in the diagram below, when using the MK2049-02 in one of the Zero Delay selections, the rising edge
of ICLK will be aligned with the rising edge of CLK2. However, the CLK1 edge in these cases will be either rising or
falling. (8 kHz is used in this illustration, but the same is true for the Zero Delay selections in the Loop Timing and
Buffer modes.)
ICLK (8 kHz)
CLK2 (MHz)
CLK1 (MHz)
Figure 1. MK2049-02 Input and Output Clock Waveforms in Zero Delay Selections
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MK2049-02SI | 51.84 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-11SITR | 56 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-11SITRLF | 56 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-11SITRLF | 56 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-11SI | 56 MHz, OTHER CLOCK GENERATOR, PDSO20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2049-03SITR | 制造商:ICS 制造商全稱:ICS 功能描述:Communications Clock PLLs |
| MK2049-03STR | 制造商:ICS 制造商全稱:ICS 功能描述:Communications Clock PLLs |
| MK2049-34 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-34A | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 Volt Communications Clock VCXO PLL |
| MK2049-34SAI | 功能描述:IC VCXO PLL CLK SYNTH 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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