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參數(shù)資料
| 型號(hào)： | MK2049-03SI |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 49.152 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封裝： | 0.300 INCH, SOIC-20 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 136K |
| 代理商： | MK2049-03SI |
MK2049-02/03
Communications Clock PLLs
MDS 2049-02/03 C
1
Revision 091801
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126 (408)295-9800tel www.icst.com
Packaged in 20 pin SOIC
Fixed input-output phase relationship on most
clock selections
Meets the TR62411, ETS300 011, and GR-1244
specification for MTIE, Pull-in/Hold-in Range,
Phase Transients, and Jitter Generation for
Stratum 3, 4, and 4E
Accept multiple inputs: 8 kHz backplane clock,
Loop Timing frequencies, or 10-28 MHz
Lock to 8 kHz ±100 ppm (External mode)
Buffer Mode allows jitter attenuation of
10–28 MHz input and x1/x0.5 or x2/x4 outputs
Exact internal ratios enable zero ppm error
Output clock rates include T1, E1, T3, E3, ISDN,
xDSL, and OC3 submultiples
5 V ±5% operation. Refer to MK2049-34 for 3.3 V
The MK2049-02 and MK2049-03 are Phase-Locked
Loop (PLL) based clock synthesizers that accept
multiple input frequencies. With an 8 kHz clock input
as a reference, the MK2049-02/03 generate T1, E1,
T3, E3, ISDN, xDSL, and other communications
frequencies. This allows for the generation of clocks
frequency-locked and phase-locked to an 8 kHz
backplane clock, simplifying clock synchronization in
communications systems. The MK2049-02/03 can
also accept a T1, E1, T3, or E3 input clock and provide
the same output for loop timing. All outputs are
frequency-locked together and to the input.
These parts also have a jitter-attenuated buffer
capability. In this mode, the MK2049-02/03 are ideal
for filtering jitter from 27 MHz video clocks or other
clocks with high jitter.
ICS can customize these devices for many other
different frequencies. Contact your ICS representative
for more details.
Block Diagram
Description
Features
VDD
GND
PLL
Clock
Synthesis,
Control, and
Jitter
Attenuation
Circuitry
Output
Buffer
Output
Buffer
External/
Loop Timing
Mux
FS3:0
ICLK
CAP1
CAP2
CLK1
CLK2
Output
Buffer
CLK3
8 kHz
(External
Mode only)
Crystal
Oscillator
Reference
Crystal
X1
X2
4
3
RESET
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MK2049-02SI | 51.84 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-11SITR | 56 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-11SITRLF | 56 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-11SITRLF | 56 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-11SI | 56 MHz, OTHER CLOCK GENERATOR, PDSO20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2049-03SITR | 制造商:ICS 制造商全稱:ICS 功能描述:Communications Clock PLLs |
| MK2049-03STR | 制造商:ICS 制造商全稱:ICS 功能描述:Communications Clock PLLs |
| MK2049-34 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-34A | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 Volt Communications Clock VCXO PLL |
| MK2049-34SAI | 功能描述:IC VCXO PLL CLK SYNTH 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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