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參數(shù)資料
| 型號： | MK2049-03SI |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 49.152 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封裝： | 0.300 INCH, SOIC-20 |
| 文件頁數(shù)： | 2/11頁 |
| 文件大?。?/td> | 136K |
| 代理商： | MK2049-03SI |
MK2049-02/03
Communications Clock PLLs
MDS 2049-02/03 C
10
Revision 091801
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126 (408)295-9800tel www.icst.com
Determining the Crystal Frequency Adjustment Capacitors
To determine the crystal adjustment capacitor values, you will need a PC board of your final layout, a frequency
counter capable of less than 1 ppm resolution and accuracy, two power supplies, and some samples of the crystals
which you plan to use in production, along with measured initial accuracy for each crystal at the specified load
capacitance, CL .
To determine the value of the crystal capacitors:
1. Connect VDD of the MK2049 to 5.0 V. Connect pin 18 of the MK2049 to the second power supply. Adjust the
voltage on pin 18 to 0.0 V. Measure and record the frequency of the CLK1 or CLK2 output .
2. Adjust the voltage on pin 18 to 3.0 V. Measure and record the frequency of the same output.
To calculate the centering error:
Centering
error
(f3.0V - ftarget) + (f0.0V - ftarget)
ftarget
errorxtal
= 106
-
Where ftarget = 44.736000 MHz, for example, and errorxtal =
actual initial accuracy (in ppm) of the
crystal being measured.
If the centering error is less than ±15 ppm, no adjustment is needed. If the centering error is more than 15 ppm
negative, the PC board has too much stray capacitance and will need to be redone with a new layout to reduce stray
capacitance. (The crystal may be re-specified to a lower load capacitance instead. Contact ICS for details.) If the
centering error is more than 15 ppm positive, add identical fixed centering capacitors from each crystal pin to ground.
The value for each of these caps (in pF) is given by:
External Capacitor = 2*(centering error)/(trim sensitivity)
Trim sensitivity is a parameter which can be supplied by your crystal vendor. If you do not know the value, assume it is
30 ppm/pF. After any changes, repeat the measurement to verify that the remaining error is acceptably low (less than
±15 ppm).
The ICS applications department can perform this procedure on your board. Call us at 408-295-9800, and we will
arrange for you to send us a PC board (stuffed or unstuffed) and one of your crystals. We will calculate the value of
capacitors needed.
LAYOUT AND EXTERNAL COMPONENTS (continued)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MK2049-02SI | 51.84 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-11SITR | 56 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-11SITRLF | 56 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-11SITRLF | 56 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-11SI | 56 MHz, OTHER CLOCK GENERATOR, PDSO20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2049-03SITR | 制造商:ICS 制造商全稱:ICS 功能描述:Communications Clock PLLs |
| MK2049-03STR | 制造商:ICS 制造商全稱:ICS 功能描述:Communications Clock PLLs |
| MK2049-34 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-34A | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 Volt Communications Clock VCXO PLL |
| MK2049-34SAI | 功能描述:IC VCXO PLL CLK SYNTH 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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