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參數(shù)資料
| 型號(hào)： | MIC2593-2BTQ TR |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 5/26頁(yè) |
| 文件大?。?/td> | 220K |
| 描述： | IC PCI HOT PLUG CTLR DUAL 48TQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類(lèi)型： | 熱交換控制器 |
| 應(yīng)用： | PCI，PCI-X |
| 內(nèi)部開(kāi)關(guān)： | 無(wú) |
| 電源電壓： | 3.3V，5V，±12V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 其它名稱(chēng)： | MIC2593-2BTQTR MIC2593-2BTQTR-ND |
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Micrel, Inc.
MIC2593
September 2008
5
M9999-092208
Pin Number
Pin Name
Pin Function
15, 22
VAUXA, VAUXB
3.3VAUX[A/B] Output to PCI Card Slot: These outputs connect the 3.3AUX pin
of the PCI connectors to VSTBY[A/B] via internal 400m& MOSFETs. These
outputs are current limited and protected against short-circuit faults.
44, 43
ONA, ONB
Enable Inputs: Rising-edge triggered. Used to enable or disable the MAINA and
MAINB (5V, 3.3V, +12V and 12V) outputs. Taking ON[A/B] low after a fault
resets the 5V, 3.3V, +12V and/or 12V fault latches for the affected slot. Tie
these pins to GND if using SMI power control. Also, see pin description for
/FAULTA and /FAULTB.
45, 42
AUXENA, AUXENB
Enable Inputs: Rising-edge triggered. Used to enable or disable VAUXA and
VAUXB outputs. Taking AUXEN[A/B] low after a fault resets the respective slots
Aux Output Fault Latch. Tie these pins to GND if using SMI power control. Also,
see pin description for /FAULTA and /FAULTB.
2, 35
CFILTERA, CFILTERB
Overcurrent Timer (Filter) Capacitor [A/B]: Capacitors connected between these
pins and GND set the duration of t
FLT
. t
FLT
is the amount of time for which a slot
remains in current limit before its circuit breaker is tripped.
1, 36
/FAULTA, /FAULTB
/FAULT[A/B] Outputs: Open-drain, active-low. Asserted whenever the circuit
breaker trips due to a fault condition (overcurrent, input undervoltage,
overtemperature). Each pin requires an external pull-up resistor to VSTBY.
Bringing the slots ON[A/B] pin low resets /FAULT[A/B] if /FAULT[A/B] was
asserted in response to a fault condition on one of the slots MAIN outputs (5V,
3.3V, +12V, or 12V).
/FAULT[A/B] is reset by bringing the slots AUXEN[A/B] pin low if /FAULT[A/B]
was asserted in response to a fault condition on the slots VAUX output. If a fault
condition occurred on both the MAIN and VAUX[A/B] outputs of the same slot,
then both ON[A/B] and AUXEN[A/B] must be brought low to de-assert the
/FAULT[A/B] output.
4, 38
GPIA, GPIB
General Purpose Inputs: The states of these two inputs are available by reading
the Common Status Register, Bits [4:5]. If not used, connect each pin to GND.
40, 41
A1, A0
SMBus Address Select Pins: Connect to ground or leave open in order to 41 A0
program device SMBus base address. These inputs have internal pull-up
resistors to VSTBY[A/B].
48
SDA
SMBus Data: Bidirectional SMBus data line.
47
SCL
SMBus Clock: Input.
37
/INT
Interrupt Output: Open-drain, active-low. Asserted whenever a power fault is
detected if the INTMSK bit (CS Register Bit D[3]) is a logical "0". This output is
de-asserted by performing an "echo reset" to the appropriate fault bit(s) in the
STAT[A/B] and/or CS registers. This pin requires an external pull-up resistor to
V
STBY
.
33, 46
GND
IC Ground Connections: Tie directly to the systems analog ground plane
directly at the device.
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