參數資料
型號: MIC2593-2BTQ TR
廠商: Micrel Inc
文件頁數: 15/26頁
文件大?。?/td> 220K
描述: IC PCI HOT PLUG CTLR DUAL 48TQFP
標準包裝: 2,000
類型: 熱交換控制器
應用: PCI,PCI-X
內部開關:
電源電壓: 3.3V,5V,±12V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP
供應商設備封裝: 48-TQFP(7x7)
包裝: 帶卷 (TR)
其它名稱: MIC2593-2BTQTR
MIC2593-2BTQTR-ND
Micrel, Inc.
MIC2593
 
September 2008 
15
M9999-092208
 
Either or both external ON[A/B] and AUXEN[A/B] input
signals are asserted, AND
"    12VIN[A/B], 12MVIN[A/B], 5VIN[A/B], 3VIN[A/B],
or VSTBY[A/B] input voltage is lower than its
respective ULVO threshold, OR
"    The fast OC circuit breaker[A/B] has tripped, OR
"    The slow OC circuit breaker[A/B] has tripped
AND its filter timeout[A/B] has expired, OR
"    The slow OC circuit breaker[A/B] has tripped
AND Slot[A/B] die temperature exceeds 140癈,
OR
"    The    MIC2593s    global    die    temperature
exceeds160癈
In order to clear /FAULT[A/B] outputs once asserted,
ON[A/B] and/or AUXEN[A/B] input signals must be de-
asserted. Please see the /FAULT[A/B] pin description for
additional information.
Hot Plug Interface (HPI) Operation
Once the input supplies are above their respective UVLO
thresholds, the Hot Plug Interface can be utilized for
power   control   by   enabling   the   control   input   pins
(AUXEN[A/B] and ON[A/B]) for each slot. In order for the
MIC2593 to switch on the VAUX supply for either slot, the
AUXEN[A/B] control must be enabled after the power-on-
reset delay, t
POR
 (typically 500祍), has elapsed. The MAIN
output supplies can also be enabled after t
POR
. The timing
response diagram of Figure 8 illustrates a Hot Plug
Interface operation where an overcurrent fault is detected
by the MIC2593 controller after initiating a power-up
sequence. The figure illustrates the output response of
/FAULT, /INT, VAUX[A/B] supplies, and an external
MOSFET control MAIN[A/B] output supply, either 3.3V or
5V.
MIC2593 SMBus Address Configuration
The MIC2593 responds to its own unique address which
is assigned using A2, A1, and A0. These represent the 3
LSBs of its 7-bit address, as shown in Table 3. These
address bits are assigned only during power up of the
VSTBY[A/B] supply input. These three bits allow up to
eight MIC2593 devices in a single system. These pins
are either grounded or left unconnected to specify a
logical 0 or 1, respectively. A pin designated as a logical
1 may also be pulled up to V
STBY
.
Serial Port Operation
The MIC2593 uses standard SMBus Write_Byte and
Read_Byte operations for communication with its host.
The SMBus Write_Byte operation involves sending the
devices slave address, with the R/W bit (LSB) set to the
low (write) state, followed by a command byte and a
data byte. The SMBus Read_Byte operation is similar,
but is a composite write and read operation: the host first
sends the devices slave address followed by the
command byte, as in a write operation. A new Start bit
must then be sent to the MIC2593, followed by a repeat
of the slave address with the R/W bit set to the high
(read) state. The data to be read from the part may then
be clocked out. There is one exception to this rule: If the
location latched in the pointer register from the last write
operation is known to be correct (i.e., points to the
desired   register   within   the   MIC2593),   then   the
Receive_Byte procedure may be used. To perform a
Receive_Byte operation, the host sends an address byte
to select the slave MIC2593, with the R/W bit set to the
high (read) state, and then retrieves the data byte.
Figures 9 through 11 show the formats for these data
read and data write procedures.
The Command Register is eight bits (one byte) wide.
This byte carries the address of the MIC2593s register
to be operated upon. The command byte values
corresponding   to   the   various   MIC2593   register
addresses are shown in Table 4. Command byte values
other than 0000 0XXXb = 00h - 07hare reserved and
should not be used.
Inputs
MIC2593 Slave Addresses
A2     A1     A0
Binary
Hex
0
0
0
1000 000
b
 
80
h
 
0
0
1
1000 001
b
 
82
h
 
0
1
0
1000 010
b
 
84
h
 
0
1
1
1000 011
b
 
86
h
 
1
0
0
1000 100
b
 
88
h
 
1
0
1
1000 101
b
 
8A
h
 
1
1
0
1000 110
b
 
8C
h
 
1
1
1
1000 111
b
 
8E
h
 
Table 3. MIC2593 SMBus Addressing
 
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