參數(shù)資料
型號(hào): MHVIC2115NR2
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: RF LDMOS Wideband Integrated Power Amplifier
中文描述: 射頻LDMOS寬帶集成功率放大器
文件頁數(shù): 1/12頁
文件大小: 425K
代理商: MHVIC2115NR2
MHVIC2115NR2
1
RF Device Data
Freescale Semiconductor
RF LDMOS Wideband Integrated
Power Amplifier
The MHVIC2115NR2 wideband integrated circuit is designed for base station
applications. It uses Freescale’s newest High Voltage (26 to 28 Volts) LDMOS
IC technology and integrates a multi-stage structure. Its wideband On-Chip
matching design makes it usable from 1600 to 2600 MHz. The linearity
performances cover W-CDMA modulation formats.
Final Application
Typical W-CDMA Performance: -45 dBc ACPR, 2110-2170 MHz, V
DD
=
27 Volts, I
DQ1
= 56 mA, I
DQ2
= 61 mA, I
DQ3
= 117 mA, P
out
= 34 dBm,
3GPP Test Model 1, Measured in 1.0 MHz BW @ 4 MHz offset, 64 DTCH
Power Gain — 30 dB
PAE = 16%
Driver Application
Typical W-CDMA Performance: -53 dBc ACPR, 2110-2170 MHz, V
DD
=
26 Volts, I
DQ1
= 96 mA, I
DQ2
= 204 mA, I
DQ3
= 111 mA, P
out
= 23 dBm,
3GPP Test Model 1, Measured in 3.84 MHz BW @ 5 MHz offset, 64 DTCH
Power Gain — 34 dB
Gain Flatness = 0.3 dB from 2110-2170 MHz
P1dB = 15 Watts, Gain Flatness = 0.2 dB from 2110-2170 MHz
Capable of Handling 3:1 VSWR, @ 26 Vdc, 2140 MHz, 15
Watts CW
Output Power
Features
Characterized with Series Equivalent Large-Signal Impedance Parameters
On-Chip Matching (50
Ohm Input, DC Blocked, >5 Ohm Output)
Integrated Temperature Compensation with Enable/Disable Function
Integrated ESD Protection
RoHS Compliant
In Tape and Reel. R2 Suffix = 1,500 Units per 16 mm, 13 inch Reel.
Table 1. Maximum Ratings
Rating
Symbol
Value
Unit
Drain-Source Voltage
V
DSS
-0.5, +65
Vdc
Gate-Source Voltage
V
GS
-0.5, +15
Vdc
Storage Temperature Range
T
stg
- 65 to +150
°
C
Operating Junction Temperature
T
J
150
°
C
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
(Top View)
9
N.C.
V
GS3
V
GS2
V
GS1
RF
in
RF
in
V
DS1
V
DS2
N.C.
V
DS3
/RF
out
V
DS3
/RF
out
V
DS3
/RF
out
V
DS3
/RF
out
V
DS3
/RF
out
V
DS3
/RF
out
N.C.
Quiescent Current
Temperature Compensation
3 Stages I
C
V
DS1
V
DS2
RF
in
I
C
V
GS3
V
GS2
V
GS1
V
DS3
/RF
out
Note: Exposed backside flag is source
terminal for transistors.
Figure 1.
Block Diagram
Figure 2. Pin Connections
Document Number: MHVIC2115NR2
Rev. 5, 5/2006
Freescale Semiconductor
Technical Data
MHVIC2115NR2
CASE 978-03
PFP-16
2170 MHz, 26 V, 23/34 dBm
W-CDMA
RF LDMOS WIDEBAND
INTEGRATED POWER AMPLIFIER
16
1
Freescale Semiconductor, Inc., 2006. All rights reserved.
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