參數(shù)資料
型號: MHVIC915NR2
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: RF LDMOS Wideband Integrated Power Amplifier
中文描述: 射頻LDMOS寬帶集成功率放大器
文件頁數(shù): 1/16頁
文件大?。?/td> 506K
代理商: MHVIC915NR2
MHVIC915NR2
1
RF Device Data
Freescale Semiconductor
RF LDMOS Wideband Integrated
Power Amplifier
The MHVIC915NR2 wideband integrated circuit is designed with on-chip
matching that makes it usable from 750 to 1000
MHz. This multi-stage
structure is rated for 26 to 28
Volt operation and covers all typical cellular base
station modulation formats.
Final Application
Typical Single-Carrier N-CDMA Performance: V
DD
= 27 Volts, I
DQ1
=
80 mA, I
DQ2
= 120 mA, P
out
= 34 dBm, Full Frequency Band (746 to
960 MHz), IS-95 CDMA (Pilot, Sync, Paging, Traffic Codes 8 Through 13)
Power Gain — 31 dB
Power Added Efficiency
— 21%
ACPR @ 750 kHz Offset — -50 dBc in 30 kHz Bandwidth
Driver Applications
Typical Single-Carrier N-CDMA Performance: V
DD
= 27 Volts, I
DQ1
= 80
mA, I
DQ2
= 120 mA, P
out
= 23 dBm, Full Frequency Band (869-
894 MHz), IS-95 CDMA (Pilot, Sync, Paging, Traffic Codes 8 Through 13),
Channel Bandwidth = 1.2288 MHz. PAR = 9.8 dB @ 0.01%
Probability on CCDF.
Power Gain — 31 dB
Power Added Efficiency
— 21%
ACPR @ 750 kHz Offset — -60 dBc in 30 kHz Bandwidth
ACPR @ 1.98 MHz Offset — -66 dBc in 30 kHz Bandwidth
Typical GSM Performance: V
DD
= 26 Volts, P
out
= 15 W P1dB, Full
Frequency Band (921-960 MHz)
Power Gain — 30 dB @ P1dB
Power Added Efficiency = 56% @ P1dB
Capable of Handling 3:1 VSWR, @ 27 Vdc, 880 MHz, 15 Watts CW
Output Power
Characterized with Series Equivalent Large-Signal Impedance Parameters
On-Chip Matching (50
Ohm Input, DC Blocked, >9 Ohm Output)
Integrated Quiescent Current Temperature Compensation with
Enable/Disable Function
On-Chip Current Mirror g
m
Reference FET for Self Biasing Application
(1)
Integrated ESD Protection
RoHS Compliant
In Tape and Reel. R2 Suffix = 1,500 Units per 16 mm, 13 inch Reel.
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
(Top View)
9
N.C.
V
DS1
GND
V
GS1
V
GS2
N.C.
V
DS2
/RF
out
V
DS2
/RF
out
V
DS2
/RF
out
V
DS2
/RF
out
V
DS2
/RF
out
V
DS2
/RF
out
N.C.
V
GS1
RF
in
V
DS1
V
GS2
RF
in
V
DS2
/RF
out
2 Stage IC
Quiescent Current
Temperature Compensation
V
RD1
V
RG1
V
RD1
V
RG1
Note: Exposed backside flag is source
terminal for transistors.
Figure 2. Pin Connections
Figure 1. Block Diagram
1. Refer to AN1987,
Quiescent Current Control for the RF Integrated Circuit Device Family.
Go to http://www.freescale.com/rf.
Select Documentation/Application Notes - AN1987.
Document Number: MHVIC915NR2
Rev. 9, 5/2006
Freescale Semiconductor
Technical Data
MHVIC915NR2
CASE 978-03
PFP-16
PLASTIC
746-960 MHz, 15 W, 27 V
SINGLE N-CDMA, GSM/GSM EDGE
RF LDMOS WIDEBAND
INTEGRATED POWER AMPLIFIER
16
1
Freescale Semiconductor, Inc., 2006. All rights reserved.
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