參數(shù)資料
型號: MDS213CG
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 網(wǎng)絡接口
英文描述: 12-Port 10/100Mbps + 1Gbps Ethernet Switch
中文描述: DATACOM, LAN SWITCHING CIRCUIT, PBGA456
封裝: 35 X 35 MM, 2.33 MM HEIGHT, MS-034, HSBGA-456
文件頁數(shù): 66/120頁
文件大?。?/td> 1678K
代理商: MDS213CG
MDS213
Data Sheet
66
Zarlink Semiconductor Inc.
4. Frame Control Buffers Management
FCBSL
FCB Stack Size Limit
740
W/R
FCBST
Frame Ctrl Buffer Stack - Buffer Low Threshold
744
W/R
BCT
Buffer Counter Threshold
74C
W/R
BCHL
Buffer Counter Hi-Low Selection
750
W/R
5. Queue Management
CINQ
CPU Input Queue
708
W/--
COTQ
CPU Output Queue
70C
-/R
6. Switching Control
HPCR
HISC Processor Control Register
6C0
W/R
HMCL0
HISC Micro-Code Loading Port-Low
6C4
W/R
HMCL1
HISC Micro-Code Loading Port-High
6C8
W/R
HPRC
HISC Priority Control Register
6D0
W/R
MCS0R
Micro Sequence 0 Register
6D4
W/R
MCS1R
Micro Sequence 1 Register
6D8
W/R
FCR
Flooding Control Register
6DC
W/R
MCAT
MCT Aging Timer
6E0
W/R
TPMXR
Trunk Port Mapping Table Index Register
6E4
W/--
TPMTD
Trunk Port Mapping Table Data Register
6E8
W/R
PTR
Pacing Time Regulation
6EC
W/R
MTCR
MCT Threshold & Counter Register
6F0
W/R
7. Link List Management
LKS
Link List Status Register
680
W/R
AMBX
Mail Box Access Port
684
W/R
AFML
Free Mail Box List Access Port
688
W/R
8. Access Control Function Group 1 (Chip Level controls)
AVTC
VLAN Type Code
648
W/R
AXSC
Transmission Scheduling Control Register
64C
W/R
ATTL
Transmission Timing & Threshold Control Register
650
W/R
AMIIC
MII Command Register
654
W/--
AMIIS
MII Status Register
658
--/R
AFCRIA
Flow Control Ram Input Address
65C
W/--
AFCRID0
Flow Control Ram Input Data
660
W/R
AFCRID1
Flow Control Ram Input Data
664
W/R
Tag
Description
Address
W/R
Table 8 - MDS212 Register Map (continued)
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