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ATmega16M1/32M1/64M1 [DATASHEET]
8209E–AVR–11/2012
19.3.3.12
Synchronization
Hard synchronization occurs on the recessive-to-dominant transition of the start bit. The bit time is restarted from
that edge.
Re-synchronization occurs when a recessive-to-dominant edge doesn't occur within the Synchronization Segment
in a message.
19.3.4
Arbitration
The CAN protocol handles bus accesses according to the concept called “Carrier Sense Multiple Access with Arbi-
tration on Message Priority”.
During transmission, arbitration on the CAN bus can be lost to a competing device with a higher priority CAN Iden-
tifier. This arbitration concept avoids collisions of messages whose transmission was started by more than one
node simultaneously and makes sure the most important message is sent first without time loss.
The bus access conflict is resolved during the arbitration field mostly over the identifier value. If a data frame and a
remote frame with the same identifier are initiated at the same time, the data frame prevails over the remote frame
(c.f. RTR bit).
Figure 19-4. Bus arbitration.
19.3.5
Errors
The CAN protocol signals any errors immediately as they occur. Three error detection mechanisms are imple-
mented at the message level and two at the bit level:
19.3.5.1
Error at message level
Cyclic Redundancy Check (CRC)
The CRC safeguards the information in the frame by adding redundant check bits at the transmission end. At
the receiver these bits are re-computed and tested against the received bits. If they do not agree there has been
a CRC error.
Frame Check
This mechanism verifies the structure of the transmitted frame by checking the bit fields against the fixed format
and the frame size. Errors detected by frame checks are designated "format errors".
ACK Errors
As already mentioned frames received are acknowledged by all receivers through positive acknowledgement. If
no acknowledgement is received by the transmitter of the message an ACK error is indicated.
19.3.5.2
Error at bit level
Monitoring
The ability of the transmitter to detect errors is based on the monitoring of bus signals. Each node which
node A
TXCAN
node B
TXCAN
ID10 ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
SOF
RTR IDE
CAN bus
- - - - - - - - -
Arbitration lost
Node A loses the bus
Node B wins the bus