27
ATmega16M1/32M1/64M1 [DATASHEET]
8209E–AVR–11/2012
8.1.5
ADC Clock – clk
ADC
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce
noise generated by digital circuitry. This gives more accurate ADC conversion results.
8.2
Clock sources
The device has the following clock source options, selectable by Flash Fuse bits as illustrated in
Table 8-1. The
clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules.
Note:
1. For all fuses “1” means unprogrammed while “0” means programmed.
2. Ext osc: external osc.
3. RC osc: internal RC oscillator.
4. Ext clk: external clock Input.
The various choices for each clocking option is given in the following sections. When the CPU wakes up from
Power-down or Power-save, the selected clock source is used to time the start-up, ensuring stable Oscillator oper-
ation before instruction execution starts. When the CPU starts from reset, there is an additional delay allowing the
power to reach a stable level before starting normal operation. The Watchdog Oscillator is used for timing this real-
time part of the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in
Table 8-2 onpage 27. The frequency of the Watchdog Oscillator is voltage dependent as shown in TBD.
8.3
Default clock source
The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed. The default clock source set-
ting is the Internal RC Oscillator with longest start-up time and an initial system clock prescaling of eight. This
Table 8-1.
Device clocking options select
Device clocking option
System
clock
PLL input
CKSEL3..0
External crystal/ceramic resonator
Ext osc
RC osc
1111 - 1000
PLL output divided by 4 : 16MHz / PLL driven by external
crystal/ceramic resonator
Ext osc
0100
PLL output divided by 4 : 16MHz / PLL driven by external
crystal/ceramic resonator
PLL/4
Ext osc
0101
Reserved
N/A
0110
Reserved
N/A
0111
PLL output divided by 4 : 16MHz
PLL/4
RC osc
0011
Calibrated internal RC oscillator
RC osc
0010
PLL output divided by 4 : 16MHz / PLL driven by external
clock
PLL/4
Ext clk
0001
External clock
Ext clk
RC osc
0000
Table 8-2.
Number of watchdog oscillator cycles.
Typical time-out (V
CC = 5.0V)
Typical time-out (V
CC = 3.0V)
Number of cycles
4.1ms
4.3ms
4K (4,096)
65ms
69ms
64K (65,536)