參數(shù)資料
型號(hào): MD80C52EXXX-20SB
廠商: ATMEL CORP
元件分類(lèi): 微控制器/微處理器
英文描述: 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CDIP40
封裝: 0.600 INCH, CERAMIC, DIP-40
文件頁(yè)數(shù): 31/198頁(yè)
文件大小: 4822K
代理商: MD80C52EXXX-20SB
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126
8111C–MCU Wireless–09/09
AT86RF231
10. Radio Transceiver Usage
This section describes basic procedures to receive and transmit frames using the AT86RF231.
For a detailed programming description refer to reference [6].
10.1
Frame Receive Procedure
A frame reception comprises of two actions: The PHY listens for, receives and demodulates the
frame to the Frame Buffer and signalizes the reception to the microcontroller. After or while that
the microcontroller read the available frame data from the Frame Buffer via the SPI interface.
While in state RX_ON or RX_AACK_ON the radio transceiver searches for incoming frames on
the selected channel. Assuming the appropriate interrupts are enabled, a detection of an
IEEE 802.15.4 compliant frame is indicated by interrupt IRQ_2 (RX_START) first. The frame
reception is completed when issuing interrupt IRQ_3 (TRX_END).
Different Frame Buffer read access scenarios are recommended for:
Waiting for IRQ_3 (TRX_END) interrupt before starting a Frame Buffer read access is recom-
mended for operations considered to be none time critical. Figure 10-1 on page 126 illustrates
the frame receive procedure using IRQ_3 (TRX_END).
Figure 10-1. Transactions between AT86RF231 and Microcontroller during Receive
Critical protocol timing could require starting the Frame Buffer read access after interrupt
IRQ_ 2 (RX_START). T he first byte of the frame data can be read 32 s afte r the
IRQ_2 (RX_START) interrupt. The microcontroller must ensure to read slower than the frame is
received. Otherwise a Frame Buffer under run occurs, IRQ_6 (TRX_UR) is issued, and the
frame data may be not valid. To avoid this, the Frame Buffer read access can be controlled by
using a Frame Buffer Empty indicator, refer to Section 11.7 “Frame Buffer Empty Indicator” on
Non-time critical applications
read access starts after IRQ_3 (TRX_END)
Time-critical applications
read access starts after IRQ_2 (RX_START)
AT
86RF
231
Mic
ro
cont
roller
IRQ issued (IRQ_2)
Read IRQ status, pin 24 (IRQ) deasserted
IRQ issued (IRQ_3)
Read frame data (Frame Buffer access)
Read IRQ status, pin 24 (IRQ) deasserted
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