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參數(shù)資料
| 型號(hào)： | MD80C52EXXX-20SB |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CDIP40 |
| 封裝： | 0.600 INCH, CERAMIC, DIP-40 |
| 文件頁(yè)數(shù)： | 156/198頁(yè) |
| 文件大?。?/td> | 4822K |
| 代理商： | MD80C52EXXX-20SB |
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60
8111C–MCU Wireless–09/09
AT86RF231
Note that this feature can be used in all scenarios, independent of other configurations. How-
ever, shorter acknowledgment timing is especially useful when using High Data Rate Modes to
increase battery lifetime and to improve the overall data throughput; refer to Section 11.3 “High
7.2.3.4
RX_AACK_NOCLK - RX_AACK_ON without CLKM
If the AT86RF231 is listening for an incoming frame and the microcontroller is not running an
application, the microcontroller can be powered down to decrease the total system power con-
sumption. This special power-down scenario for systems running in clock synchronous mode
(see Section 6. “Microcontroller Interface” on page 16) is supported by the AT86RF231 using the
state RX_AACK_ON_NOCLK. The radio transceiver functionality in this state is based on that in
state RX_AACK_ON with pin 17 (CLKM) disabled.
The RX_AACK_NOCLK state is entered from RX_AACK_ON by a rising edge at pin 11
(SLP_TR). The return to RX_AACK_ON state results either from a successful frame reception or
a falling edge on pin SLP_TR.
The CLKM pin is disabled 35 clock cycles after the rising edge at SLP_TR pin. This allows the
microcontroller to complete its power-down sequence. This is not valid for clock rates 250 kHz
and 62.5 kHz, where the main clock at pin 17 (CLKM) is switched off immediately.
In case of the reception of a valid frame, IRQ_3 (TRX_END) is issued and pin 17 (CLKM) is
turned on. A timing diagram is shown in Figure 6-16 on page 28. A received frame is considered
valid if it passes address filtering and has a correct FCS. If an ACK was requested the radio
transceiver enters BUSY_RX_AACK state and follows the procedure described in Section 7.2.3
After the transaction has been completed, the radio transceiver reenters the RX_AACK_ON
state.
The radio transceiver reenters the RX_AACK_ON_NOCLK state only, when the next rising edge
at SLP_TR pin occurs.
It is not recommended to operate the receiver in state RX_AACK_NOCLK with register bit
SLOTTED_OPERATION (register 0x2C, XAH_XTRL_0) set, refer to “Register Description -
Table 7-11.
Overview of RX_AACK Configuration Bits
Register
Register Name
Description
Address
Bit
0x17
2
AACK_ACK_TIME
0: Standard compliant acknowledgement timing
of 12 symbol periods. In slotted acknowledge-
ment operation mode, the acknowledgment
frame transmission can be triggered 6 symbol
periods after reception of the frame earliest.
1: Reduced acknowledgment timing of 2 symbol
periods (32 s).
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| MQ80C32E-30/883 | 8-BIT, 30 MHz, MICROCONTROLLER, CQFP44 |
| MR80C52CXXX-16/883R | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQCC44 |
| MR80C52TXXX-16SB | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQCC44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MD80C86 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
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| MD80C86-2/883 | 制造商:Intersil Corporation 功能描述:MPU 16BIT CMOS 8MHZ 40CDIP - Rail/Tube 制造商:Rochester Electronics LLC 功能描述:CPU 16BILT 5V CMOS 8MHZ 40CDIP - Bulk |
| MD80C86-2/B | 制造商:Intersil Corporation 功能描述:MPU 16BIT CMOS 8MHZ 40CDIP - Rail/Tube |
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