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參數(shù)資料
| 型號： | MD80C52EXXX-20SB |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CDIP40 |
| 封裝： | 0.600 INCH, CERAMIC, DIP-40 |
| 文件頁數(shù)： | 128/198頁 |
| 文件大?。?/td> | 4822K |
| 代理商： | MD80C52EXXX-20SB |
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35
8111C–MCU Wireless–09/09
AT86RF231
All digital inputs are pulled-up or pulled-down during P_ON state, refer to Section 1.3.2 “Pull-Up
and Pull-Down Configuration” on page 7. This is necessary to support microcontrollers where
GPIO signals are floating after power on or reset. The input pull-up and pull-down circuitry is dis-
abled when the radio transceiver leaves the P_ON state. Output pins DIG1/DIG2 are pulled-
down to digital ground, whereas pins DIG3/DIG4 are pulled-down to analog ground, unless their
configuration is changed.
Prior to leaving P_ON, the microcontroller must set the pins to the default operating values:
SLP_TR = L, /RST = H and /SEL = H.
All interrupts are disabled by default. Thus, interrupts for state transition control are to be
enabled first, e.g. enable IRQ_4 (AWAKE_END) to indicate a state transition to TRX_OFF state
or interrupt IRQ_0 (PLL_LOCK) to signal a locked PLL in PLL_ON state. In P_ON state a first
access to the radio transceiver registers is possible after a default 1 MHz master clock is pro-
vided at pin 17 (CLKM), refer to Table 7-1 on page 42.
Once the supply voltage has stabilized and the crystal oscillator has settled (see Section 12.5
“General RF Specifications” on page 158, parameter 12.5.7), a valid SPI write access to register
bit s T R X_CMD (r egist er 0 x 0 2 , T R X_STATE) wit h t he comma nd T R X_O FF or
FORCE_TRX_OFF initiate a state change from P_ON towards TRX_OFF state, which is then
indicated by an AWAKE_END interrupt if enabled.
7.1.2.2
SLEEP - Sleep State
In SLEEP state, the entire radio transceiver is disabled. No circuitry is operating. The radio
transceiver current consumption is reduced to leakage current only. This state can only be
entered from state TRX_OFF, by setting the pin SLP_TR = H.
If CLKM is enabled, the SLEEP state is entered 35 CLKM cycles after the rising edge at pin 11
(SLP_TR). At that time CLKM is turned off. If the CLKM output is already turned off (bits
CLKM_CTRL = 0 in register 0x03), the SLEEP state is entered immediately. At clock rates
250 kHz and 62.5 kHz, the main clock at pin 17 (CLKM) is turned off immediately.
Setting SLP_TR = L returns the radio transceiver to the TRX_OFF state. During SLEEP the reg-
ister contents remains valid while the content of the Frame Buffer and the security engine (AES)
are cleared.
/RST = L in SLEEP state returns the radio transceiver to TRX_OFF state and thereby sets all
registers to their default values. Exceptions are register bits CLKM_CTRL (register 0x03,
TRX_CTRL_0). These register bits require a specific treatment, for details see Section 9.6.4
7.1.2.3
TRX_OFF - Clock State
In TRX_OFF the crystal oscillator is running and the master clock is available at pin 17 (CLKM)
after the crystal oscillator has stabilized. The SPI interface and digital voltage regulator are
enabled, thus the radio transceiver registers, the Frame Buffer and security engine (AES) are
accessible (see Section 9.3 “Frame Buffer” on page 107 and Section 11.1 “Security Module
In contrast to P_ON state the pull-up and pull-down configuration is disabled.
Pin 11 (SLP_TR) and pin 8 (/RST) are available for state control. Note that the analog front-end
is disabled during TRX_OFF.
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