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參數(shù)資料
| 型號(hào)： | MCV14AI/SL |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDSO14 |
| 封裝： | 3.90 MM, PLASTIC, SOIC-4 |
| 文件頁(yè)數(shù)： | 48/84頁(yè) |
| 文件大?。?/td> | 1007K |
| 代理商： | MCV14AI/SL |
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MCV14A
DS41338B-page 50
Preliminary
2009 Microchip Technology Inc.
8.1.5
SLEEP
This ADC does not have a dedicated ADC clock, and
therefore, no conversion in Sleep is possible. If a
conversion is underway and a Sleep command is
executed, the GO/DONE and ADON bit will be cleared.
This will stop any conversion in process and power-
down the ADC module to conserve power. Due to the
nature of the conversion process, the ADRES may con-
tain a partial conversion. At least 1 bit must have been
converted prior to Sleep to have partial conversion data
in ADRES. The ADCS and CHS bits are reset to their
default condition; ANS<1:0> = 11 and CHS<1:0> = 11.
For accurate conversions, TAD must meet the
following:
500 ns < TAD < 50
μs
TAD = 1/(FOSC/divisor)
Shaded areas indicate TAD out of range for accurate
conversions. If analog input is desired at these
frequencies, use INTOSC/8 for the ADC clock source.
TABLE 8-2:
TAD FOR ADCS SETTINGS WITH VARIOUS OSCILLATORS
TABLE 8-3:
EFFECTS OF SLEEP ON ADCON0
Source
ADCS
<1:0>
Divisor
20
MHz
16
MHz
8MHz 4MHz 1MHz
500
kHz
350
kHz
200
kHz
100
kHz
32 kHz
INTOSC
11
4
—
—.5
μs1 μs
—
FOSC
10
4
.2
μs
.25
μs.5 μs1 μs4 μs8 μs11 μs20 μs40 μs
125
μs
FOSC
01
8
.4
μs.5 μs1 μs2 μs8 μs16 μs23 μs40 μs
80
μs
250
μs
FOSC
00
16
.8
μs1 μs2 μs4 μs16 μs32 μs46 μs
80
μs 160 μs 500 μs
ANS1
ANS0
ADCS1
ADCS0
CHS1
CHS0
GO/DONE
ADON
Entering
Sleep
Unchanged Unchanged
111
100
Wake or
Reset
11
111
100
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