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參數(shù)資料
| 型號： | MCV14AI/SL |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDSO14 |
| 封裝： | 3.90 MM, PLASTIC, SOIC-4 |
| 文件頁數(shù)： | 14/84頁 |
| 文件大?。?/td> | 1007K |
| 代理商： | MCV14AI/SL |
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2009 Microchip Technology Inc.
Preliminary
DS41338B-page 19
MCV14A
4.0
FLASH DATA MEMORY
The data memory is the Flash data memory block,
which attaches to the user Flash program memory. It is
located at addresses 0x400-0x43F, as shown in Figure
5-1.
This Flash data memory block consists of 8 rows and
has self-write capability of up to 64 bytes. This memory
block is not directly mapped in the register file space.
Instead, it is indirectly addressed through the Special
Function Registers. There are three SFRs used to read
and write this memory:
EEDATA (Register 4-1)
EEADR (Register 4-2)
EECON (Register 4-3)
EEDATA holds the 8-bit data for read/write, and
EEADR holds the address of the EEDATA location
being accessed. The effective program counter is
EEADR + 400h with only the lower 8 bits of each word
being readable or writable.
EEADR = 00h, PC = 400h
EEADR = 01h, PC = 401h
The Flash data memory allows byte read and write, and
during the operations of read and write cycles, the CPU
stalls.
The timing for all self-writes and erases is controlled by
the internal timing block of the program memory (see
Table 11-11). The write/erase voltages are generated
by an on-chip charge pump rated to operate over the
voltage range of the device for byte or word operations.
When the device is code-protected, the CPU may
continue to read and write the Flash data memory and
read the program memory. When code-protected, the
device programmer can no longer access data or
program memory.
REGISTER 4-1:
EEDATA: FLASH DATA REGISTER
R/W-x
EEDATA7
EEDATA6
EEDATA5
EEDATA4
EEDATA3
EEDATA2
EEDATA1
EEDATA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
EEDATA<7:0>: 8-bits of data to be read from/written to data Flash
REGISTER 4-2:
EEADR: FLASH ADDRESS REGISTER
U-0
R/W-x
—
EEADR5
EEADR4
EEADR3
EEADR2
EEADR1
EEADR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Do not use
bit 5-0
EEADR<5:0>: 6-bits of data to be read from/written to data Flash
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PDF描述 |
|---|---|
| MCV14ATI/SL | 8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDSO14 |
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| MD8031AHB883B | 8-BIT, 12 MHz, MICROCONTROLLER, CDIP40 |
| MD8255A | 24 I/O, PIA-GENERAL PURPOSE, PDIP40 |
| MD82C52-/883 | 1 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, CDIP28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCV15/10-GF-381 | 制造商:Phoenix Contact 功能描述:HEADER PCB VERTICAL 3.81MM 10WAY |
| MCV15/2-GF-381 | 制造商:Phoenix Contact 功能描述:HEADER PCB VERTICAL 3.81MM 2WAY |
| MCV15/3-GF-381 | 制造商:Phoenix Contact 功能描述:HEADER PCB VERTICAL 3.81MM 3WAY |
| MCV15/4-GF-381 | 制造商:Phoenix Contact 功能描述:HEADER PCB VERTICAL 3.81MM 4WAY |
| MCV15/5-GF-381 | 制造商:Phoenix Contact 功能描述:HEADER PCB VERTICAL 3.81MM 5WAY |
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