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參數(shù)資料
| 型號： | MCP3221 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 560KBITS BRAM 400000 SYSTEM GATES 404 I/ - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 低功耗12位A / D轉(zhuǎn)換器具有I2C⑩接口 |
| 文件頁數(shù)： | 16/27頁 |
| 文件大?。?/td> | 520K |
| 代理商： | MCP3221 |
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MCP3221
DS21732B-page 16
2003 Microchip Technology Inc.
5.2
Device Addressing
The address byte is the first byte received following the
START condition from the master device. The first part
of the control byte consists of a 4-bit device code,
which is set to
1010
for the MCP3221. The device code
is followed by three address bits: A2, A1 and A0. The
default address bits are
1001
. Contact the Microchip
factory for additional address bit options. The address
bits allow up to eight MCP3221 devices on the same
bus and are used to determine which device is
accessed.
The eighth bit of the slave address determines if the
master device wants to read conversion data or write to
the MCP3221. When set to a ‘
1
’, a read operation is
selected. When set to a ‘
0
’, a write operation is
selected. There are no writable registers on the
MCP3221. Therefore, this bit must be set to a ’
1
’ in
order to initiate a conversion.
The MCP3221 is a slave device that is compatible with
the I
2
C 2-wire serial interface protocol. A hardware
connection diagram is shown in Figure 6-2. Communi-
cation is initiated by the microcontroller (master
device), which sends a START bit followed by the
address byte.
On completion of the conversion(s) performed by the
MCP3221, the microcontroller must send a STOP bit to
end communication.
The last bit in the device address byte is the R/W bit.
When this bit is a logic ‘
1
’, a conversion will be exe-
cuted. Setting this bit to logic ‘
0
’ will also result in an
“acknowledge” (ACK) from the MCP3221, with the
device then releasing the bus. This can be used for
device polling. Refer to Section 6.3, “Device Polling”,
for more information.
FIGURE 5-2:
Device Addressing.
5.3
Executing a Conversion
This section will describe the details of communicating
with the MCP3221 device. Initiating the sample-and-
hold acquisition, reading the conversion data and
executing multiple conversions will be discussed.
5.3.1
INITIATING THE SAMPLE AND
HOLD
The acquisition and conversion of the input signal
begins with the falling edge of the R/W bit of the
address byte. At this point, the internal clock initiates
the sample, hold and conversion cycle, all of which are
internal to the ADC.
FIGURE 5-3:
Address Byte.
Initiating the Conversion,
FIGURE 5-4:
Continuous Conversions.
Initiating the Conversion,
START
READ/WRITE
SLAVE
ADDRESS
R/W
A
1
0
0
1
1
0
1
Address Bits
(1)
Note 1:
Contact Microchip for additional address bits.
Device Code
1
2
3
4
5
6
7
8
9
SCL
SDA
1
0
0
1
A2 A1 A0 R/W
A
Start
Bit
Address Byte
Address bits
Device bits
t
ACQ
+ t
CONV
is
initiated here
SCL
SDA
D3 D2 D2
A
Lower Data Byte (n)
t
ACQ
+ t
CONV
is
initiated here
D6 D5 D4
D0
D7
A
D8
17 18 19 20 21 22 23 24 25 26
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