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| 型號： | MCP2510T-E/P |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PDIP18 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-18 |
| 文件頁數(shù)： | 56/76頁 |
| 文件大?。?/td> | 1076K |
| 代理商： | MCP2510T-E/P |
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MCP2510
DS21291C-page 6
Preliminary
1999 Microchip Technology Inc.
1.3
CAN Protocol Engine
The CAN protocol engine combines several functional
blocks, shown in Figure 1-4. These blocks and their
functions are described below.
1.4
Protocol Finite State Machine
The heart of the engine is the Finite State Machine
(FSM). This state machine sequences through mes-
sages on a bit by bit basis, changing states as the fields
of the various frame types are transmitted or received.
The FSM is a sequencer controlling the sequential data
stream between the TX/RX Shift Register, the CRC Reg-
ister, and the bus line. The FSM also controls the Error
Management Logic (EML) and the parallel data stream
between the TX/RX Shift Registers and the buffers. The
FSM insures that the processes of reception, arbitration,
transmission, and error signaling are performed accord-
ing to the CAN protocol. The automatic retransmission of
messages on the bus line is also handled by the FSM.
1.5
Cyclic Redundancy Check
The Cyclic Redundancy Check Register generates the
Cyclic Redundancy Check (CRC) code which is trans-
mitted after either the Control Field (for messages with
0 data bytes) or the Data Field, and is used to check the
CRC field of incoming messages.
1.6
Error Management Logic
The Error Management Logic is responsible for the fault
confinement of the CAN device. Its two counters, the
Receive Error Counter (REC) and the Transmit Error
Counter (TEC), are incremented and decremented by
commands from the Bit Stream Processor. According to
the values of the error counters, the CAN controller is set
into the states error-active, error-passive or bus-off.
1.7
Bit Timing Logic
The Bit Timing Logic (BTL) monitors the bus line input
and handles the bus related bit timing according to the
CAN protocol. The BTL synchronizes on a recessive to
dominant bus transition at Start of Frame (hard syn-
chronization) and on any further recessive to dominant
bus line transition if the CAN controller itself does not
transmit a dominant bit (resynchronization). The BTL
also provides programmable time segments to com-
pensate for the propagation delay time, phase shifts,
and to define the position of the Sample Point within the
bit time. The programming of the BTL depends upon
the baud rate and external physical delay times.
FIGURE 1-4:
CAN Protocol Engine Block Diagram
Bit Timing Logic
CRC<14:0>
Comparator
Receive<7:0>
Transmit<7:0>
Sample<2:0>
Majority
Decision
StuffReg<5:0>
Comparator
Transmit Logic
Receive
Error Counter
Transmit
Error Counter
Protocol
FSM
Rx
SAM
BusMon
Rec/Trm Addr.
RecData<7:0>
TrmData<7:0>
Shift<14:0>
(Transmit<5:0>, Receive<7:0>)
Tx
REC
TEC
ErrPas
BusOff
Interface to Standard Buffer
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MCP2510T-I/SO | 功能描述:網(wǎng)絡控制器與處理器 IC Stand-alone CAN RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| MCP2510T-I/ST | 功能描述:網(wǎng)絡控制器與處理器 IC Stand-alone CAN RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| MCP2515 | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:Stand-Alone CAN Controller With SPI Interface |
| MCP2515_12 | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:Stand-Alone CAN Controller with SPI Interface |
| MCP2515DM-BM | 功能描述:網(wǎng)絡開發(fā)工具 CAN Bus Monitor Demo Board RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
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