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| 型號： | MCP2510T-E/P |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PDIP18 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-18 |
| 文件頁數(shù)： | 41/76頁 |
| 文件大?。?/td> | 1076K |
| 代理商： | MCP2510T-E/P |
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MCP2510
DS21291C-page 46
Preliminary
1999 Microchip Technology Inc.
7.6
Error Interrupt
When the error interrupt is enabled (CANINTE.ERRIE
= 1) an interrupt is generated on the INT pin if an over-
flow condition occurs or if the error state of transmitter
or receiver has changed. The Error Flag Register
(EFLG) will indicate one of the following conditions.
7.6.1
RECEIVER OVERFLOW
An overflow condition occurs when the MAB has assem-
bled a valid received message (the message meets the
criteria of the acceptance filters) and the receive buffer
associated with the filter is not available for loading of a
new message. The associated EFLG.RXNOVR bit will
be set to indicate the overflow condition. This bit must be
cleared by the MCU.
7.6.2
RECEIVER WARNING
The receive error counter has reached the MCU warn-
ing limit of 96.
7.6.3
TRANSMITTER WARNING
The transmit error counter has reached the MCU warn-
ing limit of 96.
7.6.4
RECEIVER ERROR-PASSIVE
The receive error counter has exceeded the error- pas-
sive limit of 127 and the device has gone to error- pas-
sive state.
7.6.5
TRANSMITTER ERROR-PASSIVE
The transmit error counter has exceeded the error-
passive limit of 127 and the device has gone to error-
passive state.
7.6.6
BUS-OFF
The transmit error counter has exceeded 255 and the
device has gone to bus-off state.
7.7
Interrupt Acknowledge
Interrupts are directly associated with one or more sta-
tus flags in the CANINTF register. Interrupts are pend-
ing as long as one of the flags is set. Once an interrupt
flag is set by the device, the flag can not be reset by the
MCU until the interrupt condition is removed.
REGISTER 7-1:
CANINTE - Interrupt Enable Register (ADDRESS: 2Bh)
R/W-0
MERRE
WAKIE
ERRIE
TX2IE
TX1IE
TX0IE
RX1IE
RX0IE
R = Readable bit
W = Writable bit
C = Bit can be cleared by
MCU but not set
U = Unimplemented -
reads as ‘0’
- n = Value at POR reset
bit 7
bit 0
bit 7:
MERRE: Message Error Interrupt Enable
0 = Disabled
1 = Interrupt on error during message reception or transmission
bit 6:
WAKIE: Wakeup Interrupt Enable
0 = Disabled
1 = Interrupt on CAN bus activity
bit 5:
ERRIE: Error Interrupt Enable (multiple sources in EFLG register)
0 = Disabled
1 = Interrupt on EFLG error condition change
bit 4:
TX2IE: Transmit Buffer 2 Empty Interrupt Enable
0 = Disabled
1 = Interrupt on TXB2 becoming empty
bit 3:
TX1IE: Transmit Buffer 1 Empty Interrupt Enable
0 = Disabled
1 = Interrupt on TXB1 becoming empty
bit 2:
TX0IE: Transmit Buffer 0 Empty Interrupt Enable
0 = Disabled
1 = Interrupt on TXB0 becoming empty
bit 1:
RX1IE: Receive Buffer 1 Full Interrupt Enable
0 = Disabled
1 = Interrupt when message received in RXB1
bit 0:
RX0IE: Receive Buffer 0 Full Interrupt Enable
0 = Disabled
1 = Interrupt when message received in RXB0
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