參數(shù)資料
型號(hào): MCP2510-I/P
廠商: Microchip Technology
文件頁(yè)數(shù): 69/80頁(yè)
文件大小: 0K
描述: IC CAN CONTRLER IND TEMP 18DIP
產(chǎn)品培訓(xùn)模塊: CAN Bus Protection
標(biāo)準(zhǔn)包裝: 25
控制器類型: CAN 接口
接口: SPI
電源電壓: 3 V ~ 5.5 V
電流 - 電源: 10mA
工作溫度: -40°C ~ 85°C
安裝類型: 通孔
封裝/外殼: 18-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 18-PDIP
包裝: 管件
產(chǎn)品目錄頁(yè)面: 685 (CN2011-ZH PDF)
配用: DV251001-ND - KIT DEVELOPMENT CAN MCP2510
其它名稱: Q731310
2009 Microchip Technology Inc.
DS39637D-page 71
PIC18F2480/2580/4480/4580
6.2
PIC18 Instruction Cycle
6.2.1
CLOCKING SCHEME
The microcontroller clock input, whether from an inter-
nal or external source, is internally divided by four to
generate four non-overlapping quadrature clocks (Q1,
Q2, Q3 and Q4). Internally, the Program Counter (PC)
is incremented on every Q1; the instruction is fetched
from the program memory and latched into the Instruc-
tion Register (IR) during Q4. The instruction is decoded
and executed during the following Q1 through Q4. The
clocks and instruction execution flow are shown in
6.2.2
INSTRUCTION FLOW/PIPELINING
An “Instruction Cycle” consists of four Q cycles: Q1
through Q4. The instruction fetch and execute are
pipelined in such a manner that a fetch takes one
instruction cycle, while the decode and execute take
another instruction cycle. However, due to the
pipelining, each instruction effectively executes in one
cycle. If an instruction causes the program counter to
change (e.g., GOTO), then two cycles are required to
complete the instruction (Example 6-3).
A fetch cycle begins with the program counter
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 6-3:
CLOCK/INSTRUCTION CYCLE
EXAMPLE 6-3:
INSTRUCTION PIPELINE FLOW
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Q3
Q4
PC
OSC2/CLKO
(RC mode)
PC
PC + 2
PC + 4
Fetch INST (PC)
Execute INST (PC – 2)
Fetch INST (PC + 2)
Execute INST (PC)
Fetch INST (PC + 4)
Execute INST (PC + 2)
Internal
Phase
Clock
Note:
All instructions are single cycle, except for any program branches. These take two cycles since the
fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then
executed.
TCY0TCY1TCY2TCY3TCY4TCY5
1. MOVLW 55h
Fetch 1
Execute 1
2. MOVWF PORTB
Fetch 2
Execute 2
3. BRA
SUB_1
Fetch 3
Execute 3
4. BSF
PORTA, BIT3 (Forced NOP)
Fetch 4
Flush (NOP)
5. Instruction @ address SUB_1
Fetch SUB_1 Execute SUB_1
相關(guān)PDF資料
PDF描述
ENC28J60-I/SO IC ETHERNET CTRLR W/SPI 28SOIC
ENC28J60/SS IC ETHERNET CTRL 8K W/SPI 28SSOP
D38999/20MG75PN CONN RCPT 4POS WALL MNT W/PINS
V48C28M75BG CONVERTER MOD DC/DC 28V 75W
D38999/20JG75PA CONN RCPT 4POS WALL MNT W/PINS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MCP2510ISO 制造商:Microchip Technology Inc 功能描述:
MCP2510-ISO 制造商:Microchip Technology Inc 功能描述:
MCP2510-IST 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:Stand-Alone CAN Controller with SPI Interface
MCP2510I-ST 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:Stand-Alone CAN Controller with SPIa?¢ Interface
MCP2510T-/P 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:Stand-Alone CAN Controller with SPI⑩ Interface